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authorDaniel Lustig <dlustig@nvidia.com>2021-09-15 13:17:28 -0400
committerDaniel Lustig <dlustig@nvidia.com>2021-09-15 13:17:28 -0400
commit775fb545d050463e5bd8443d57b28d6760627238 (patch)
treefcef09698c4b82d2a8bc8a4eb56539fc1d572278
parent2ce79d5e432bf74fcf0c9298493431b05fafe379 (diff)
parent8dc97756189c64b8e721e1c59d4e27fccc18ffd0 (diff)
downloadriscv-isa-manual-Svinval.zip
riscv-isa-manual-Svinval.tar.gz
riscv-isa-manual-Svinval.tar.bz2
Merge branch 'Svpbmt' into SvinvalSvinval
-rw-r--r--src/supervisor.tex24
1 files changed, 3 insertions, 21 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex
index 4c919fe..fc523d6 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -2321,32 +2321,14 @@ physical page to exist simultaneously with different memory attributes. It is
also possible for a U-mode or S-mode mapping through a PTE with Svpbmt enabled
to observe different memory attributes for a given region of physical memory
than a concurrent access to the same page performed by M-mode or when
-MODE=Bare. In such cases, there may be a loss of coherence and/or of normal
-RVWMO, RVTSO, or I/O ordering semantics, and platform-specific mechanisms must
-be used to restore coherence and memory ordering.
+MODE=Bare. In such cases, the behaviors dictated by the attributes may be
+violated, and platform-specific mechanisms must be used to restore the
+expected behaviors.
\begin{commentary}
-For example, a cacheable access may be issued at the same time as a
-non-cacheable access to the same physical memory address. In this case,
-if the former is performed first in the global memory order, then it will
-be evicted from the cache by the latter. If on the other hand the cacheable
-access appears after the non-cacheable access, then the former may remain
-cached as it normally would.
-
The forthcoming Zicbom extension and the FENCE instruction will collectively
form a standard mechanism for restoring coherence in scenarios with
mismatched page attributes.
-
-Likewise, accesses performed under memory indicating the non-idempotent
-attribute must not be merged with idempotent accesses to the same region
-in flight at the same time, as the non-idempotency of the former must
-be respected. This is not expected to be a common situation.
-
-Note that Svpbmt cannot be used to completely prevent speculative reads from
-being performed to a region of memory for which the PMAs indicate idempotence,
-as speculation can still be performed via M-mode or via Bare mappings, which do
-not use the PBMTs. Platform-specific mechanisms must be used to avoid this
-form of conflict.
\end{commentary}
\begin{commentary}