summaryrefslogtreecommitdiff
path: root/p
AgeCommit message (Expand)AuthorFilesLines
2020-10-14unconditionally clear mie registerSandeep Rajendran1-1/+1
2020-04-14encoding: add new VCSR for vector 0.9Chih-Min Chao1-1/+2
2020-03-04Initialize x registers in p, pm, pt rather than just v (#21)Andrew Waterman1-1/+35
2020-02-24Fix #17 (#18)Paul Donahue1-2/+0
2019-11-28rvv: add mstatus.vs definition and initial mcaroChih-Min Chao1-0/+16
2019-11-28fill exit syscall information to make semihosting workChih-Min Chao1-0/+4
2018-09-23Avoid writing reserved values to pmpaddr CSRAndrew Waterman1-1/+2
2017-11-27Rename sptbr to satpAndrew Waterman1-2/+2
2017-07-03Fix physical load address for recent binutilspriv-1.10Andrew Waterman1-3/+6
2017-05-01Set ELF entry point correctlyAndrew Waterman1-0/+1
2017-03-30New PMP encodingAndrew Waterman1-1/+1
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman1-3/+3
2017-03-24Clean up physical memory test init codeAndrew Waterman1-5/+20
2017-03-24Avoid misa in physical memory testsAndrew Waterman1-2/+2
2017-03-23Rely on assembler to provide PMP CSRsAndrew Waterman1-2/+2
2017-03-21Use gp for TESTNUM, so compiled C code won't touch itAndrew Waterman1-1/+1
2017-03-21Set up PMP if presentAndrew Waterman1-3/+6
2017-03-09WIP on priv-1.10Andrew Waterman1-5/+8
2017-03-02Check XLEN only after initializing mtvecAndrew Waterman1-1/+1
2016-12-06avoid non-standard predefined macrosAndrew Waterman1-1/+1
2016-08-15add ALIGN after .tohost to prevent placing MMIO and data on same page (#3)Sagar Karandikar1-1/+1
2016-07-11Align mtvec to support RVCAndrew Waterman1-0/+1
2016-07-07Delegate interrupts to supervisor for supervisor testsAndrew Waterman1-0/+5
2016-05-25Keep tohost/fromhost at deterministic addressAndrew Waterman2-1/+4
2016-05-02Stop using mtohost/mfromhost registersAndrew Waterman1-2/+7
2016-04-30ERET -> xRET; change memory mapAndrew Waterman2-13/+17
2016-03-02WIP on priv spec v1.9Andrew Waterman1-5/+4
2016-02-28WIP on priv spec v1.9Andrew Waterman2-40/+35
2015-09-28make sure TESTNUM is initializedHoward Mao1-0/+1
2015-09-20Remove Hwacha v3 supportAndrew Waterman1-27/+0
2015-07-17don't pass fpu/vector tests when fpu/vector not presentYunsup Lee1-10/+1
2015-06-23Avoid "csrw stvec" if stvec_handler doesn't exist.Christopher Celio1-1/+2
2015-05-19Improve coverage of VM testsAndrew Waterman1-2/+0
2015-05-11Initialize FCSRAndrew Waterman1-1/+1
2015-05-09Update to privileged architecture version 1.7Andrew Waterman2-69/+18
2015-04-03Don't assume initial values of mstatus.ua/saAndrew Waterman1-5/+15
2015-03-30Don't rely on mstatus.fs to test FPU presenceAndrew Waterman1-9/+11
2015-03-25add mtvec_handler to machine traps from user landYunsup Lee1-11/+22
2015-03-24Don't assume PRV1/2 and IE1/2 are resetAndrew Waterman1-2/+4
2015-03-17relay hwacha cause/aux to scause/sbadaddrYunsup Lee1-1/+11
2015-03-17Merge [shm]call into ecall, [shm]ret into eretAndrew Waterman1-7/+7
2015-03-16clean up pt and vector environmentsYunsup Lee1-3/+17
2015-03-12Use hcall instead of mcallAndrew Waterman1-6/+6
2015-03-12Update to new privileged specAndrew Waterman2-15/+77
2015-01-09Add LICENSEAndrew Waterman1-0/+2
2015-01-04Avoid deprecated "b" pseudo-op; use "j" insteadAndrew Waterman1-2/+2
2014-03-03need to modify status register *before* enabling interruptsYunsup Lee1-2/+2
2014-02-25make physical timer env work againYunsup Lee1-0/+2
2014-01-31Support RV32S testsAndrew Waterman1-0/+5
2014-01-31Use TESTNUM instead of x28 directlyAndrew Waterman1-7/+5
generated by cgit v1.1 at 2024-06-30 11:42:08 +0000