diff options
-rw-r--r-- | encoding.h | 23 | ||||
-rw-r--r-- | p/riscv_test.h | 6 | ||||
-rw-r--r-- | v/vm.c | 10 |
3 files changed, 22 insertions, 17 deletions
@@ -147,9 +147,8 @@ #define IRQ_HOST 13 #define DEFAULT_RSTVEC 0x00001000 -#define DEFAULT_NMIVEC 0x00001004 -#define DEFAULT_MTVEC 0x00001010 -#define CONFIG_STRING_ADDR 0x0000100C +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 #define EXT_IO_BASE 0x40000000 #define DRAM_BASE 0x80000000 @@ -959,17 +958,20 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f #define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_FETCH_ACCESS 0x1 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 #define CAUSE_BREAKPOINT 0x3 #define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_LOAD_ACCESS 0x5 #define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_STORE_ACCESS 0x7 #define CAUSE_USER_ECALL 0x8 #define CAUSE_SUPERVISOR_ECALL 0x9 #define CAUSE_HYPERVISOR_ECALL 0xa #define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf #endif #ifdef DECLARE_INSN DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) @@ -1451,15 +1453,18 @@ DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) #endif #ifdef DECLARE_CAUSE DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) -DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) -DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) -DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) +DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) +DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) #endif diff --git a/p/riscv_test.h b/p/riscv_test.h index 9ed6ebc..708bc4d 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -153,9 +153,9 @@ reset_vector: \ la t0, stvec_handler; \ beqz t0, 1f; \ csrw stvec, t0; \ - li t0, (1 << CAUSE_FAULT_LOAD) | \ - (1 << CAUSE_FAULT_STORE) | \ - (1 << CAUSE_FAULT_FETCH) | \ + li t0, (1 << CAUSE_LOAD_PAGE_FAULT) | \ + (1 << CAUSE_STORE_PAGE_FAULT) | \ + (1 << CAUSE_FETCH_PAGE_FAULT) | \ (1 << CAUSE_MISALIGNED_FETCH) | \ (1 << CAUSE_USER_ECALL) | \ (1 << CAUSE_BREAKPOINT); \ @@ -127,7 +127,7 @@ void handle_fault(uintptr_t addr, uintptr_t cause) if (!(user_l3pt[addr/PGSIZE] & PTE_A)) { user_l3pt[addr/PGSIZE] |= PTE_A; } else { - assert(!(user_l3pt[addr/PGSIZE] & PTE_D) && cause == CAUSE_FAULT_STORE); + assert(!(user_l3pt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT); user_l3pt[addr/PGSIZE] |= PTE_D; } flush_page(addr); @@ -178,7 +178,7 @@ void handle_trap(trapframe_t* tf) assert(!"illegal instruction"); tf->epc += 4; } - else if (tf->cause == CAUSE_FAULT_FETCH || tf->cause == CAUSE_FAULT_LOAD || tf->cause == CAUSE_FAULT_STORE) + else if (tf->cause == CAUSE_FETCH_PAGE_FAULT || tf->cause == CAUSE_LOAD_PAGE_FAULT || tf->cause == CAUSE_STORE_PAGE_FAULT) handle_fault(tf->badvaddr, tf->cause); else assert(!"unexpected exception"); @@ -243,9 +243,9 @@ void vm_boot(uintptr_t test_addr) write_csr(sscratch, pa2kva(read_csr(mscratch))); write_csr(medeleg, (1 << CAUSE_USER_ECALL) | - (1 << CAUSE_FAULT_FETCH) | - (1 << CAUSE_FAULT_LOAD) | - (1 << CAUSE_FAULT_STORE)); + (1 << CAUSE_FETCH_PAGE_FAULT) | + (1 << CAUSE_LOAD_PAGE_FAULT) | + (1 << CAUSE_STORE_PAGE_FAULT)); // FPU on; accelerator on; allow supervisor access to user memory access write_csr(mstatus, MSTATUS_FS | MSTATUS_XS | MSTATUS_SUM); write_csr(mie, 0); |