riscv-tools/riscv-tests/env.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
master	Support setting V-env LFSR bits with a compiler flag (#43)	Jerry Zhao	11 months
priv-1.10	Fix physical load address for recent binutils	Andrew Waterman	7 years
priv-1.9	Support RV32 virtual memory tests	Andrew Waterman	8 years
riscv-test-env-sail	created a branch for the sail-riscv testing env	William McSpaddden	6 weeks
vectorless	disable vector trap handling	Howard Mao	9 years


Age	Commit message	Author	Files	Lines
2017-07-03	Fix physical load address for recent binutilspriv-1.10	Andrew Waterman	1	-3/+6
2017-05-05	bump encoding.h	Andrew Waterman	1	-0/+3
2017-05-01	Set ELF entry point correctly	Andrew Waterman	3	-11/+9
2017-03-30	New PMP encoding	Andrew Waterman	3	-7/+8
2017-03-29	Test sstatus.SUM more thoroughly by keeping it usually disabled	Andrew Waterman	1	-1/+6
2017-03-27	Separate page faults from physical memory access exceptions	Andrew Waterman	3	-17/+22
2017-03-24	Clean up physical memory test init code	Andrew Waterman	1	-5/+20
2017-03-24	Avoid misa in physical memory tests	Andrew Waterman	1	-2/+2
2017-03-23	Align mtvec target	Andrew Waterman	1	-0/+1
2017-03-23	Rely on assembler to provide PMP CSRs	Andrew Waterman	2	-7/+6
[...]