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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-23 12:30:59 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-23 12:30:59 -0700 |
| commit | e2e2a7111e6b357cb5ce677b97f45fa5dcdd01b9 (patch) | |
| tree | 96709eff66561c2ae82db76223c1eb6189e9d15c | |
| parent | 286b047fbe29a7c54448c88dac025f78d38681a9 (diff) | |
| download | env-e2e2a7111e6b357cb5ce677b97f45fa5dcdd01b9.zip env-e2e2a7111e6b357cb5ce677b97f45fa5dcdd01b9.tar.gz env-e2e2a7111e6b357cb5ce677b97f45fa5dcdd01b9.tar.bz2 | |
Rely on assembler to provide PMP CSRs
| -rw-r--r-- | p/riscv_test.h | 4 | ||||
| -rw-r--r-- | v/vm.c | 9 |
2 files changed, 6 insertions, 7 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h index 52d7fe9..e28c5e5 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -58,9 +58,9 @@ csrw mtvec, t0; \ csrwi sptbr, 0; \ li t0, -1; /* Set up a PMP to permit all accesses */ \ - csrw CSR_PMPADDR0, t0; \ + csrw pmpaddr0, t0; \ li t0, PMP_EN | PMP_NAPOT | PMP_M | PMP_R | PMP_W | PMP_X; \ - csrw CSR_PMPCFG0, t0; \ + csrw pmpcfg0, t0; \ 1: #define RVTEST_ENABLE_SUPERVISOR \ @@ -231,12 +231,11 @@ void vm_boot(uintptr_t test_addr) // Set up PMPs if present, ignoring illegal instruction trap if not. uintptr_t pmpc = PMP_EN | PMP_NAPOT | PMP_M | PMP_R | PMP_W | PMP_X; asm volatile ("la t0, 1f\n\t" - "csrw mtvec, t0\n\t" - "csrw %2, %3\n\t" - "csrw %0, %1\n\t" + "csrrw t0, mtvec, t0\n\t" + "csrw pmpaddr0, %1\n\t" + "csrw pmpcfg0, %0\n\t" "1:" - :: "i" (CSR_PMPCFG0), "r" (pmpc), "i" (CSR_PMPADDR0), "r" (-1) - : "t0"); + : : "r" (pmpc), "r" (-1UL) : "t0"); // set up supervisor trap handling write_csr(stvec, pa2kva(trap_entry)); |