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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-12 22:21:22 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-14 00:28:13 -0700 |
| commit | 7a4e59980705b52c705c36b4ed54a55faa4ab48a (patch) | |
| tree | 6d814d564fca1500a2f0d0bda28dd7ec042a9d11 | |
| parent | 48c6d7cfcad3a20640bfe1ec2247c26003a3b6b7 (diff) | |
| download | env-7a4e59980705b52c705c36b4ed54a55faa4ab48a.zip env-7a4e59980705b52c705c36b4ed54a55faa4ab48a.tar.gz env-7a4e59980705b52c705c36b4ed54a55faa4ab48a.tar.bz2 | |
encoding: add new vector instruction in spec 0.9
1. add rtz rounding instructions
2. add vfslide instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | encoding.h | 27 |
1 files changed, 27 insertions, 0 deletions
@@ -932,6 +932,10 @@ #define MASK_VFSGNJN_VF 0xfc00707f #define MATCH_VFSGNJX_VF 0x28005057 #define MASK_VFSGNJX_VF 0xfc00707f +#define MATCH_VFSLIDE1UP_VF 0x38005057 +#define MASK_VFSLIDE1UP_VF 0xfc00707f +#define MATCH_VFSLIDE1DOWN_VF 0x3c005057 +#define MASK_VFSLIDE1DOWN_VF 0xfc00707f #define MATCH_VFMV_S_F 0x42005057 #define MASK_VFMV_S_F 0xfff0707f #define MATCH_VFMERGE_VFM 0x5c005057 @@ -1052,6 +1056,10 @@ #define MASK_VFCVT_F_XU_V 0xfc0ff07f #define MATCH_VFCVT_F_X_V 0x88019057 #define MASK_VFCVT_F_X_V 0xfc0ff07f +#define MATCH_VFCVT_RTZ_XU_F_V 0x88031057 +#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f +#define MATCH_VFCVT_RTZ_X_F_V 0x88039057 +#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f #define MATCH_VFWCVT_XU_F_V 0x88041057 #define MASK_VFWCVT_XU_F_V 0xfc0ff07f #define MATCH_VFWCVT_X_F_V 0x88049057 @@ -1062,6 +1070,10 @@ #define MASK_VFWCVT_F_X_V 0xfc0ff07f #define MATCH_VFWCVT_F_F_V 0x88061057 #define MASK_VFWCVT_F_F_V 0xfc0ff07f +#define MATCH_VFWCVT_RTZ_XU_F_V 0x88071057 +#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f +#define MATCH_VFWCVT_RTZ_X_F_V 0x88079057 +#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f #define MATCH_VFNCVT_XU_F_W 0x88081057 #define MASK_VFNCVT_XU_F_W 0xfc0ff07f #define MATCH_VFNCVT_X_F_W 0x88089057 @@ -1074,6 +1086,10 @@ #define MASK_VFNCVT_F_F_W 0xfc0ff07f #define MATCH_VFNCVT_ROD_F_F_W 0x880a9057 #define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f +#define MATCH_VFNCVT_RTZ_XU_F_W 0x880b1057 +#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f +#define MATCH_VFNCVT_RTZ_X_F_W 0x880b9057 +#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f #define MATCH_VFSQRT_V 0x8c001057 #define MASK_VFSQRT_V 0xfc0ff07f #define MATCH_VFCLASS_V 0x8c081057 @@ -1558,6 +1574,8 @@ #define MASK_VAMOMINUE_V 0xf800707f #define MATCH_VAMOMAXUE_V 0xe000702f #define MASK_VAMOMAXUE_V 0xf800707f +#define MATCH_VMVNFR_V 0x9e003057 +#define MASK_VMVNFR_V 0xfe00707f #define CSR_FFLAGS 0x1 #define CSR_FRM 0x2 #define CSR_FCSR 0x3 @@ -2195,6 +2213,8 @@ DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF) DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF) DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF) DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF) +DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF) +DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF) DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F) DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM) DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F) @@ -2255,17 +2275,23 @@ DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V) DECLARE_INSN(vfcvt_x_f_v, MATCH_VFCVT_X_F_V, MASK_VFCVT_X_F_V) DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V) DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V) +DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V) +DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V) DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V) DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V) DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V) DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V) DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V) +DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V) +DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V) DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W) DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W) DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W) DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W) DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W) DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W) +DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W) +DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W) DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V) DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V) DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV) @@ -2508,6 +2534,7 @@ DECLARE_INSN(vamomine_v, MATCH_VAMOMINE_V, MASK_VAMOMINE_V) DECLARE_INSN(vamomaxe_v, MATCH_VAMOMAXE_V, MASK_VAMOMAXE_V) DECLARE_INSN(vamominue_v, MATCH_VAMOMINUE_V, MASK_VAMOMINUE_V) DECLARE_INSN(vamomaxue_v, MATCH_VAMOMAXUE_V, MASK_VAMOMAXUE_V) +DECLARE_INSN(vmvnfr_v, MATCH_VMVNFR_V, MASK_VMVNFR_V) #endif #ifdef DECLARE_CSR DECLARE_CSR(fflags, CSR_FFLAGS) |