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authorAndrew Waterman <andrew@sifive.com>2017-11-27 14:35:33 -0800
committerAndrew Waterman <andrew@sifive.com>2017-11-27 14:35:33 -0800
commit68cad7baf3ed0a4553fffd14726d24519ee1296a (patch)
tree029cff935fdb82221ae8e35f596bfda68495418c
parent1b76fd1f1c63dfe4cea93f426434a7384d2bf801 (diff)
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Rename sptbr to satp
-rw-r--r--encoding.h40
-rw-r--r--p/riscv_test.h4
-rw-r--r--v/vm.c6
3 files changed, 25 insertions, 25 deletions
diff --git a/encoding.h b/encoding.h
index 8ec1345..c109ce1 100644
--- a/encoding.h
+++ b/encoding.h
@@ -113,19 +113,19 @@
#define PRV_H 2
#define PRV_M 3
-#define SPTBR32_MODE 0x80000000
-#define SPTBR32_ASID 0x7FC00000
-#define SPTBR32_PPN 0x003FFFFF
-#define SPTBR64_MODE 0xF000000000000000
-#define SPTBR64_ASID 0x0FFFF00000000000
-#define SPTBR64_PPN 0x00000FFFFFFFFFFF
+#define SATP32_MODE 0x80000000
+#define SATP32_ASID 0x7FC00000
+#define SATP32_PPN 0x003FFFFF
+#define SATP64_MODE 0xF000000000000000
+#define SATP64_ASID 0x0FFFF00000000000
+#define SATP64_PPN 0x00000FFFFFFFFFFF
-#define SPTBR_MODE_OFF 0
-#define SPTBR_MODE_SV32 1
-#define SPTBR_MODE_SV39 8
-#define SPTBR_MODE_SV48 9
-#define SPTBR_MODE_SV57 10
-#define SPTBR_MODE_SV64 11
+#define SATP_MODE_OFF 0
+#define SATP_MODE_SV32 1
+#define SATP_MODE_SV39 8
+#define SATP_MODE_SV48 9
+#define SATP_MODE_SV57 10
+#define SATP_MODE_SV64 11
#define PMP_R 0x01
#define PMP_W 0x02
@@ -177,12 +177,12 @@
# define MSTATUS_SD MSTATUS64_SD
# define SSTATUS_SD SSTATUS64_SD
# define RISCV_PGLEVEL_BITS 9
-# define SPTBR_MODE SPTBR64_MODE
+# define SATP_MODE SATP64_MODE
#else
# define MSTATUS_SD MSTATUS32_SD
# define SSTATUS_SD SSTATUS32_SD
# define RISCV_PGLEVEL_BITS 10
-# define SPTBR_MODE SPTBR32_MODE
+# define SATP_MODE SATP32_MODE
#endif
#define RISCV_PGSHIFT 12
#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
@@ -790,9 +790,9 @@
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142
-#define CSR_SBADADDR 0x143
+#define CSR_STVAL 0x143
#define CSR_SIP 0x144
-#define CSR_SPTBR 0x180
+#define CSR_SATP 0x180
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
#define CSR_MEDELEG 0x302
@@ -803,7 +803,7 @@
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
-#define CSR_MBADADDR 0x343
+#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
@@ -1282,9 +1282,9 @@ DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
DECLARE_CSR(sscratch, CSR_SSCRATCH)
DECLARE_CSR(sepc, CSR_SEPC)
DECLARE_CSR(scause, CSR_SCAUSE)
-DECLARE_CSR(sbadaddr, CSR_SBADADDR)
+DECLARE_CSR(stval, CSR_STVAL)
DECLARE_CSR(sip, CSR_SIP)
-DECLARE_CSR(sptbr, CSR_SPTBR)
+DECLARE_CSR(satp, CSR_SATP)
DECLARE_CSR(mstatus, CSR_MSTATUS)
DECLARE_CSR(misa, CSR_MISA)
DECLARE_CSR(medeleg, CSR_MEDELEG)
@@ -1295,7 +1295,7 @@ DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
DECLARE_CSR(mscratch, CSR_MSCRATCH)
DECLARE_CSR(mepc, CSR_MEPC)
DECLARE_CSR(mcause, CSR_MCAUSE)
-DECLARE_CSR(mbadaddr, CSR_MBADADDR)
+DECLARE_CSR(mtval, CSR_MTVAL)
DECLARE_CSR(mip, CSR_MIP)
DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
diff --git a/p/riscv_test.h b/p/riscv_test.h
index baad787..3fbcb50 100644
--- a/p/riscv_test.h
+++ b/p/riscv_test.h
@@ -63,7 +63,7 @@
.align 2; \
1:
-#define INIT_SPTBR \
+#define INIT_SATP \
la t0, 1f; \
csrw mtvec, t0; \
csrwi sptbr, 0; \
@@ -142,7 +142,7 @@ handle_exception: \
j write_tohost; \
reset_vector: \
RISCV_MULTICORE_DISABLE; \
- INIT_SPTBR; \
+ INIT_SATP; \
INIT_PMP; \
DELEGATE_NO_TRAPS; \
li TESTNUM, 0; \
diff --git a/v/vm.c b/v/vm.c
index 6ab7fd1..a2e5533 100644
--- a/v/vm.c
+++ b/v/vm.c
@@ -225,13 +225,13 @@ void vm_boot(uintptr_t test_addr)
l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
kernel_l2pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
user_l2pt[0] = ((pte_t)user_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
- uintptr_t vm_choice = SPTBR_MODE_SV39;
+ uintptr_t vm_choice = SATP_MODE_SV39;
#else
l1pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
- uintptr_t vm_choice = SPTBR_MODE_SV32;
+ uintptr_t vm_choice = SATP_MODE_SV32;
#endif
write_csr(sptbr, ((uintptr_t)l1pt >> PGSHIFT) |
- (vm_choice * (SPTBR_MODE & ~(SPTBR_MODE<<1))));
+ (vm_choice * (SATP_MODE & ~(SATP_MODE<<1))));
// Set up PMPs if present, ignoring illegal instruction trap if not.
uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X;