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| author | Andrew Waterman <andrew@sifive.com> | 2023-03-16 17:02:49 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-03-16 17:02:49 -0700 |
| commit | 4fabfb4e0d3eacc1dc791da70e342e4b68ea7e46 (patch) | |
| tree | 0e385137fcee6dac636682eb586da8b1d6ca15e9 | |
| parent | 91754f96c020bc9ff0bb206ea8ee9a102ee9c842 (diff) | |
| download | env-4fabfb4e0d3eacc1dc791da70e342e4b68ea7e46.zip env-4fabfb4e0d3eacc1dc791da70e342e4b68ea7e46.tar.gz env-4fabfb4e0d3eacc1dc791da70e342e4b68ea7e46.tar.bz2 | |
Cope with presence of Smrnmi extension
Enable RNMIs if the extension is present, as the feature affects trap
behavior when RNMIs are masked.
| -rw-r--r-- | p/riscv_test.h | 8 | ||||
| -rw-r--r-- | v/entry.S | 2 |
2 files changed, 10 insertions, 0 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h index a8c50c7..7bf35cf 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -107,6 +107,13 @@ .align 2; \ 1: +#define INIT_RNMI \ + la t0, 1f; \ + csrw mtvec, t0; \ + csrwi CSR_MNSTATUS, MNSTATUS_NMIE; \ + .align 2; \ +1: + #define INIT_SATP \ la t0, 1f; \ csrw mtvec, t0; \ @@ -197,6 +204,7 @@ handle_exception: \ reset_vector: \ INIT_XREG; \ RISCV_MULTICORE_DISABLE; \ + INIT_RNMI; \ INIT_SATP; \ INIT_PMP; \ DELEGATE_NO_TRAPS; \ @@ -60,6 +60,8 @@ handle_reset: li x30, 0 li x31, 0 + INIT_RNMI + la t0, trap_vector csrw mtvec, t0 la sp, STACK_TOP - SIZEOF_TRAPFRAME_T |