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| author | Andrew Waterman <andrew@sifive.com> | 2020-10-14 19:22:02 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-10-14 19:22:02 -0700 |
| commit | 43d3d53809085e2c8f030d72eed1bdf798bfb31a (patch) | |
| tree | 35e37c88a6560fe6337bef73fe22cc8ea70194f1 | |
| parent | 4d4a4352f4dbd8149af956e30579d9e14860a5a7 (diff) | |
| parent | 1a3f249075292b9746897a69f3ba6eb2e7835141 (diff) | |
| download | env-43d3d53809085e2c8f030d72eed1bdf798bfb31a.zip env-43d3d53809085e2c8f030d72eed1bdf798bfb31a.tar.gz env-43d3d53809085e2c8f030d72eed1bdf798bfb31a.tar.bz2 | |
Merge pull request #26 from SandeepRajendran/master
Unconditionally clear mie register while disabling interrupts.
| -rw-r--r-- | p/riscv_test.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h index 88ca6c1..2b6ff83 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -115,11 +115,11 @@ 1: #define DELEGATE_NO_TRAPS \ + csrwi mie, 0; \ la t0, 1f; \ csrw mtvec, t0; \ csrwi medeleg, 0; \ csrwi mideleg, 0; \ - csrwi mie, 0; \ .align 2; \ 1: |