aboutsummaryrefslogtreecommitdiff
path: root/debug/targets/RISC-V/spike-1.cfg
blob: c6c7d2d8847288ceef8150abe09d0fd81909bc5b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
adapter speed     10000

adapter driver remote_bitbang
remote_bitbang host $::env(REMOTE_BITBANG_HOST)
remote_bitbang port $::env(REMOTE_BITBANG_PORT)

set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913

set _TARGETNAME $_CHIPNAME.cpu
if {$::env(USE_FREERTOS)} {
    target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos FreeRTOS
} else {
    target create $_TARGETNAME riscv -chain-position $_TARGETNAME
}
$_TARGETNAME configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1

gdb_report_data_abort enable
gdb_report_register_access_error enable

# Expose an unimplemented CSR so we can test non-existent register access
# behavior.
riscv expose_csrs 2288
riscv expose_custom 1,12345-12348

init

set challenge [riscv authdata_read]
riscv authdata_write [expr {$challenge + 1}]

halt

arm semihosting enable