| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2018-08-21 | Changing the register mstatus is read into (#152) | Srivatsa Yogendra | 1 | -2/+2 |
| 2018-08-20 | Revert "Fix to solve the failing tests shamt, csr and scall (#151)" | Andrew Waterman | 1 | -32/+4 |
| 2018-08-17 | Fix to solve the failing tests shamt, csr and scall (#151) | Srivatsa Yogendra | 1 | -4/+32 |
| 2017-11-22 | Check sepc for rv64si/scall test. (#107) | Christopher Celio | 1 | -0/+4 |
| 2017-11-09 | Make rv64mi-p-ecall work when U-mode is not present | Andrew Waterman | 1 | -1/+17 |
| 2017-10-30 | Declare trap handlers as global symbols. (#87) | Richard Xia | 1 | -0/+1 |
| 2016-07-11 | Remove instruction width assumptions to support RVC | Andrew Waterman | 1 | -0/+1 |
| 2016-04-30 | ERET -> xRET; new memory map | Andrew Waterman | 1 | -1/+3 |
| 2016-03-03 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -9/+12 |
| 2015-05-09 | Update to privileged architecture version 1.7 | Andrew Waterman | 1 | -1/+3 |
| 2015-03-25 | split out S-mode tests and M-mode tests | Yunsup Lee | 1 | -3/+8 |
| 2015-03-21 | Merge rv64si and rv32si tests | Andrew Waterman | 1 | -0/+43 |
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index : riscv-tools/riscv-tests.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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