riscv-tools/riscv-tests.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-02-20	Fix rv64mi-p-csr on systems with FPUs	Andrew Waterman	1	-2/+3
2020-01-31	Added CSR test cases on whether writing 0 to CSR works, as that might get ove...	Torbjørn Viem Ness	1	-0/+2
2017-11-09	Use mstatus.MPP to check existence of U-mode	Andrew Waterman	1	-5/+6
2017-10-30	Declare trap handlers as global symbols. (#87)	Richard Xia	1	-0/+1
2017-10-26	Fix rv64mi-csr for the case where U-mode is not available. (#86)	Richard Xia	1	-0/+16
2017-08-07	rv64[ms]i-csr: Only emit F instructions when compiled for F.	Richard Xia	1	-1/+6
2017-05-05	Check UXL in sstatus	Andrew Waterman	1	-0/+5
2016-11-01	Make sure FP stores don't write memory if mstatus.FS=0.	Andrew Waterman	1	-8/+22
2016-08-26	Update to new breakpoint & counter spec	Andrew Waterman	1	-6/+6
2016-07-22	skip user-mode trap tests in rv32mi/rv64mi-p-csr if no user mode	Howard Mao	1	-0/+9
2016-07-11	Remove instruction width assumptions to support RVC	Andrew Waterman	1	-0/+1
2016-04-30	ERET -> xRET; new memory map	Andrew Waterman	1	-16/+8
2016-03-03	Some S-mode tests really only belong in M-mode	Andrew Waterman	1	-1/+9
2016-03-03	WIP on priv spec v1.9	Andrew Waterman	1	-11/+6
2015-05-09	Update to privileged architecture version 1.7	Andrew Waterman	1	-2/+2
2015-03-25	split out S-mode tests and M-mode tests	Yunsup Lee	1	-7/+14
2015-03-17	Merge [shm]call into ecall, [shm]ret into eret	Andrew Waterman	1	-1/+1
2015-03-12	Update to new privileged spec	Andrew Waterman	1	-23/+30
2015-01-09	Add LICENSE	Andrew Waterman	1	-0/+2
2014-01-31	Add rv32si tests, including illegality of shamt[5]	Andrew Waterman	1	-1/+1
2014-01-31	Make CSR test much more robust	Andrew Waterman	1	-0/+52
2014-01-21	Add CSRRx/CSRRxI test	Andrew Waterman	1	-0/+33