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2023-06-30debug: Don't rely on RISCV envTim Newsome2-8/+4
2023-06-30Fix for https://github.com/riscv-software-src/riscv-tests/issues/482Tommy Murphy1-2/+2
2023-06-29debug: pylint fix.Tim Newsome1-2/+2
2023-06-29Merge pull request #480 from riscv-software-src/pylintTim Newsome1-4/+7
2023-06-29Add --target-timeout to debug test script.Tim Newsome1-1/+7
2023-06-29Merge pull request #478 from Du-Chao/masterTim Newsome1-4/+16
2023-06-27Pylint fixes.Tim Newsome1-4/+7
2023-06-27Merge pull request #477 from MarekVCodasip/test-exclusionTim Newsome4-1/+52
2023-06-27Add a way to exclude tests by specifying an exclusion fileMarek Vrbka4-1/+52
2023-06-15debug: optimize the FreeRtosTest case.Chao Du1-4/+16
2023-06-12Get gcc and gdb path from environment.Tim Newsome1-7/+10
2023-05-25debug: New pylint => new warnings => new cleanupsTim Newsome4-24/+34
2023-05-10New pylint, so make everything clean again.Tim Newsome2-61/+8
2023-05-01Update OpenOCD cfg files to new syntaxTim Newsome7-34/+34
2023-03-01Fix intermittent IcountTest failure on multi hart.Tim Newsome1-1/+1
2023-02-28Merge pull request #458 from Du-Chao/masterTim Newsome1-2/+2
2023-02-21debug: fix pylint error W0621 redefined-outer-nameChao Du1-2/+2
2023-02-16Add test for icount triggers.Tim Newsome1-0/+27
2023-02-02Fix EtriggerTest on multi-hart targets.Tim Newsome1-0/+1
2023-01-06debug: Add Itrigger test.Tim Newsome1-0/+26
2023-01-06debug: Tweak interrupt.c, so a test can run to exit()Tim Newsome1-1/+4
2022-12-29debug: Add etrigger test.Tim Newsome2-1/+20
2022-12-14debug: Add CeaseRunTestTim Newsome1-0/+23
2022-12-14debug: Add CeaseStepiTest.Tim Newsome2-3/+37
2022-12-14debug: Create CeaseMultiTest. (#436)Tim Newsome2-2/+55
2022-12-14debug: Remove unnecessary exit() functions. (#437)Tim Newsome3-11/+4
2022-12-08Fix regression in VcsSim introduced by #334 (#440)Jerry Zhao1-0/+1
2022-12-01debug: Disassemble memory when a failure happens. (#432)Tim Newsome1-1/+1
2022-12-01`flush regs` -> `maintenance flush register-cache` (#431)Tim Newsome1-1/+1
2022-12-01debug: Park unused harts with a cease instruction. (#434)Tim Newsome3-2/+23
2022-12-01Share exit() among more tests. (#433)Tim Newsome3-16/+9
2022-11-10SvNNTest needs 32KB of RAM. (#428)Tim Newsome2-4/+7
2022-11-04Make MulticoreRegTest work with real hardware.Tim Newsome2-17/+19
2022-11-03Fix PrivChange test address comparison. (#427)Tim Newsome1-3/+4
2022-10-26Specify trigger type=2 in trigger.S (#425)YenHaoChen1-2/+3
2022-10-24Increase timeouts for multi-spike test. (#423)Tim Newsome2-3/+4
2022-10-21Change memory address used in debug tests. (#422)Tim Newsome4-3/+3
2022-10-20Merge pull request #421 from riscv-software-src/pylintTim Newsome1-1/+2
2022-10-12Fix long line to make pylint happy.Tim Newsome1-1/+2
2022-10-12Get coverage of progbuf FPR accesses.Tim Newsome3-2/+9
2022-10-07debug: Add --debug_server arg to open gdb on OpenOCDTim Newsome2-3/+14
2022-10-06Merge pull request #414 from YenHaoChen/pr-timestampTim Newsome1-2/+2
2022-10-05Update testlib.py; remove ANSI escape sequencesYenHaoChen1-1/+2
2022-10-05update gdbserver.py; release tolerance value of MemorySampleTest()YenHaoChen1-2/+2
2022-07-25Ignore `mip` and `time` in DisconnectTest. (#406)Tim Newsome1-1/+2
2022-07-22Fix string formatting in testlib.assertTrue()Tim Newsome1-1/+1
2022-07-14Pylint fix. (#405)Tim Newsome1-1/+2
2022-07-14Only run SemihostingFileio on single hart systems. (#404)Tim Newsome1-0/+11
2022-07-11Debug MemorySampleMixed: Disable 64-bit sampling on 32-bit targets (#402)Luke Wren1-2/+6
2022-07-08Fix SemihostingFileio (#403)Tim Newsome1-1/+2
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