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| author | Jerry Zhao <qwertyuiopghb@gmail.com> | 2022-12-08 23:47:14 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-12-08 23:47:14 -0800 |
| commit | 45f4da6224ee254f235ff223f77e69dccf100c46 (patch) | |
| tree | f62f66ea770c0afe131f3b530cf60b202d229bc7 /debug | |
| parent | 5cbc01f45d9876ec84e8229d4c3898c96597e431 (diff) | |
| download | riscv-tests-45f4da6224ee254f235ff223f77e69dccf100c46.zip riscv-tests-45f4da6224ee254f235ff223f77e69dccf100c46.tar.gz riscv-tests-45f4da6224ee254f235ff223f77e69dccf100c46.tar.bz2 | |
Fix regression in VcsSim introduced by #334 (#440)
Diffstat (limited to 'debug')
| -rw-r--r-- | debug/testlib.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/debug/testlib.py b/debug/testlib.py index f8e3d8c..d2e587b 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -240,6 +240,7 @@ class VcsSim: # pylint: disable-next=consider-using-with logfile = tempfile.NamedTemporaryFile(prefix='simv', suffix='.log') logname = logfile.name + lognames = [logname] def __init__(self, sim_cmd=None, debug=False, timeout=300): if sim_cmd: |