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2018-02-09Test resuming from a trigger.resume_from_triggerTim Newsome3-10/+9
2018-02-07Link scripts shouldn't be executable.Tim Newsome1-0/+0
2018-01-08Deal with gdb reporting pmpcfg0 not existing.Tim Newsome2-3/+16
It's an optional register.
2018-01-05Add test for multicore failureTim Newsome2-5/+40
Specifically, make sure that after resuming all cores, and halting core 0, that OpenOCD's poll() doesn't mess up the currently selected hart to the point where memory accesses intended for core 0 go to core 1.
2017-12-27Test FPRs that aren't XLEN in size.Tim Newsome6-8/+20
Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
2017-12-21Add all-tests target.Tim Newsome1-1/+3
I hope to use this in riscv-tools' regression.sh.
2017-12-20Remove `set arch riscv:rv%d`Tim Newsome1-1/+0
gdb gets target XLEN from register width now, so this is taken care of automatically.
2017-12-20Verify that F18 does not exist on FPU-less targetsTim Newsome1-17/+20
2017-12-12Display env variables used when invoking OpenOCDTim Newsome1-1/+6
This makes it a little easier to just cut and paste from the log when reproducing a failure. (The port number still needs changing though.)
2017-12-01Ensure there are no unnamed registers.Tim Newsome1-0/+2
2017-11-30Clean up VcsSim init()Tim Newsome1-2/+12
Use a unique log file, so you can run multiple instances at once. Add time out to waiting for the simulator to be ready.
2017-11-27Rename sbadaddr to satpAndrew Waterman1-3/+3
2017-11-19Ensure log file is fully written before reading itTim Newsome1-0/+1
Fixes --print-failures sometimes not actually printing out details about failures.
2017-11-19Make pylint happy.Tim Newsome3-12/+16
2017-11-17debug: Fix the XLEN command line checkxlen_fixMegan Wachs1-7/+8
2017-11-16Debug: Use the --32 and --64 command line arguments (#97)Megan Wachs3-10/+17
* Debug: Actually use the --32 and --64 command line arguments * debug: make XLEN mismatch message clearer
2017-11-16Disable PMP for PrivRw test.Tim Newsome1-0/+5
2017-11-15Clarify PrivTest detail.Tim Newsome1-0/+2
2017-11-02Add --print-log-names to print temp log names ASAPTim Newsome2-5/+17
When not passed, they are no longer printed out.
2017-11-02Ensure gdb connection failures end up in main log.Tim Newsome1-9/+18
2017-11-02debug: Need to apply remotetimeout before connecting to remote target (#94)Megan Wachs1-6/+7
* debug: Need to apply remotetimeout before connecting to remote target * debug: whitespace cleanup
2017-11-01Make pylint 1.6.5 happy.Tim Newsome4-6/+5
2017-11-01Test register aliases in the simple register testsTim Newsome1-9/+17
2017-11-01Fix MulticoreRegTest.Tim Newsome2-59/+65
This test would fail intermittently if gdb on the first hart managed to set a breakpoint, resume, halt, and clear the breakpoint before the second hart got a chance to resume.
2017-10-31Temporarily comment out MulticoreRegTest due to flakiness.Richard Xia1-57/+58
2017-10-24Increase dual-core RV64 timeouts.Tim Newsome2-2/+2
I need this for CompareSections to pass when I instrument spike to be really slow.
2017-10-19Get helpful gdb output in MemTestBlock.Tim Newsome1-1/+4
2017-10-12Pay attention to server_timeout_secTim Newsome1-2/+3
Fixes #83.
2017-10-04Resurrect priv tests.Tim Newsome1-52/+51
2017-10-04Merge pull request #79 from riscv/multigdbTim Newsome13-96/+236
Multigdb support
2017-09-29Make ExamineTarget multi-core aware.Tim Newsome1-18/+23
Now on multi-core targets it only runs once, wasting less time.
2017-09-29Fix tests to work in multi-gdb mode.Tim Newsome13-87/+236
The Gdb class now can handle connecting to more than one gdb. It enumerates the harts across all connections, and when asked to select a hart, it transparently sends future gdb commands to the correct instance. Multicore tests still have to be aware of some differences. The main one is that when executing 'c' in RTOS mode, all harts resume, while in multi-gdb mode only the current one resumes. Additionally, gdb doesn't set breakpoints until 'c' is issued, so the hart where breakpoints are set needs to be resumed before other harts might see them.
2017-09-22Remove unused function.Tim Newsome1-9/+0
2017-09-21Add coverage for single-core non-rtos OpenOCD.Tim Newsome4-3/+19
2017-09-19Allow multiple reset vectors.Tim Newsome4-3/+8
Some boards have jumpers that control the reset vector, and forcing them one way or another is more annoying than dealing with it in software.
2017-09-19Merge pull request #76 from riscv/multicoreTim Newsome3-14/+28
Add interrupts to MulticoreRunHaltStepiTest.
2017-09-19Forgot to commit this earlier.Tim Newsome1-0/+20
Fixes #77.
2017-09-18Add interrupts to MulticoreRunHaltStepiTest.Tim Newsome4-16/+29
Just to hammer on anything at once, and hopefully catch weird interactions if they exist.
2017-09-15Don't read entire log into RAM just to print it.Tim Newsome1-2/+1
2017-09-14misa is stored in the hart now, not the targetTim Newsome1-6/+6
2017-09-14When spike fails to launch, display its output.Tim Newsome1-21/+29
2017-09-14Test debugging code with interrupts.Tim Newsome5-4/+80
2017-09-14Call postMortem() when a test fails.Tim Newsome1-0/+10
2017-09-14Clarify timeout units.Tim Newsome1-0/+1
2017-09-01Add some infrastructure for multicore tests.Tim Newsome5-40/+61
When compiling, define the number of harts. This means we only need to allocate a lot of stack if there are a lot of harts.
2017-09-01Use 32-bit link script for 32-bit target.Tim Newsome1-1/+1
2017-08-28This file isn't ready yet.Tim Newsome1-11/+0
2017-08-28Forgot to add this file.Tim Newsome1-0/+81
2017-08-28Increase remotetimeout for spike targets.Tim Newsome5-0/+15
On overloaded systems, when executing compare-sections, otherwise gdb might hit a timeout and the compare-sections code doesn't deal with it. (You get an error message complaining that 130 is not a valid hex digit.)
2017-08-28Fix rebase bug.Tim Newsome1-1/+3
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