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riscv-tools/riscv-tests.git
attempt-travis-fix
ceasetest2
compliance_tests
cs152-sp18-lab3
debug
debug-0.13
debug-clear-satp
debug-delete-sim
debug_auth
debug_disassemble
disable_unavailable
dma-memcpy
eos20-bringup
hw_watchpoint
interrupts
master
misc
no_progbuf
priv
privchange-dontdeleteme
python3
rekall
resume_from_trigger
riscv-tests-sail
rtos
rvt-master
smi-demo
split-isa-tests
sqrt-171
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Author
Files
Lines
2018-10-05
Make HwWatchpoint test fail on incorrect result.
hw_watchpoint
Tim Newsome
3
-7
/
+10
2018-10-03
Added tests for hw and sw watchpoints
cgsfv
3
-0
/
+88
2018-09-13
Assert if HiFive1 program is too large.
Tim Newsome
1
-0
/
+2
2018-09-13
Put debug test stack in data instead of text
Tim Newsome
1
-0
/
+1
2018-09-03
Merge pull request #156 from riscv/PrivChange
Tim Newsome
1
-27
/
+26
2018-08-31
Fix CustomRegisterTest.
Tim Newsome
2
-5
/
+6
2018-08-29
Add test case for `riscv expose_custom`.
Tim Newsome
12
-0
/
+55
2018-08-28
Reset address translation/perms before PrivChange
Tim Newsome
1
-27
/
+26
2018-08-27
Neuter TriggerStoreAddressInstant
Tim Newsome
1
-1
/
+13
2018-08-27
Make pylint happy.
Tim Newsome
1
-1
/
+2
2018-08-25
Temporarily disabling PrivChange test
Andrew Waterman
1
-22
/
+23
2018-08-23
Make pylint happy with change d1d2d953b5016b465.
Tim Newsome
2
-3
/
+4
2018-08-23
Get all of the log into the final log file
Tim Newsome
1
-6
/
+20
2018-08-23
Merge pull request #153 from dmitryryzhov/rtos-switch-active-thread
Tim Newsome
1
-0
/
+28
2018-08-22
Disable MulticoreRunHaltStepiTest
Tim Newsome
1
-52
/
+52
2018-08-22
Add debug test, which checks that openocd correctly switch active thread on a...
Dmitry Ryzhov
1
-0
/
+28
2018-08-13
Add jump/hbreak test.
Tim Newsome
1
-0
/
+23
2018-07-03
rwatch/watch on explicit address
Tim Newsome
1
-2
/
+4
2018-06-18
Add reproduce line to the end of debug test logs
Tim Newsome
1
-0
/
+2
2018-05-18
Fix MulticoreRunHaltStepiTest
Tim Newsome
2
-23
/
+46
2018-05-14
Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-single
Megan Wachs
2
-21
/
+11
2018-05-14
Make DownloadTest properly park other harts.
Tim Newsome
2
-5
/
+9
2018-05-14
debug: remove some unintentionally added newlines
Megan Wachs
1
-2
/
+0
2018-05-14
debug: Fixing the non-RTOS behavior for DownloadTest
Megan Wachs
1
-7
/
+16
2018-05-11
debug: mark more tests as single-hart tests
Megan Wachs
1
-6
/
+13
2018-05-11
debug: output some more useful info into the post-mortem data
Megan Wachs
1
-0
/
+5
2018-04-30
Fix formatting to make pylint happy.
Tim Newsome
1
-5
/
+6
2018-04-27
debug: need to clear satp before changing priv
debug-clear-satp
Megan Wachs
1
-0
/
+7
2018-04-27
Merge pull request #125 from riscv/debug-delete-sim
Megan Wachs
1
-17
/
+0
2018-04-27
debug: add missing align directive on trap_entry
trap_entry_align-1
Megan Wachs
1
-0
/
+1
2018-04-24
Fix race when making logs directory
Tim Newsome
1
-1
/
+5
2018-04-19
Delete E300Sim.py
debug-delete-sim
Megan Wachs
1
-17
/
+0
2018-04-09
Compute gdb command timeout based on ops estimate
Tim Newsome
2
-14
/
+18
2018-04-02
Use `gdb_report_register_access_error enable`
Tim Newsome
4
-0
/
+6
2018-03-27
Test debug authentication.
Tim Newsome
4
-3
/
+19
2018-03-23
Print log filename at the end of the log.
Tim Newsome
1
-0
/
+1
2018-03-01
Test debugging with/without a program buffer
Tim Newsome
5
-5
/
+10
2018-03-01
Ensure an error when reading a non-existent CSR.
Tim Newsome
5
-0
/
+29
2018-02-09
Test resuming from a trigger.
resume_from_trigger
Tim Newsome
3
-10
/
+9
2018-02-07
Link scripts shouldn't be executable.
Tim Newsome
1
-0
/
+0
2018-01-08
Deal with gdb reporting pmpcfg0 not existing.
Tim Newsome
2
-3
/
+16
2018-01-05
Add test for multicore failure
Tim Newsome
2
-5
/
+40
2017-12-27
Test FPRs that aren't XLEN in size.
Tim Newsome
6
-8
/
+20
2017-12-21
Add all-tests target.
Tim Newsome
1
-1
/
+3
2017-12-20
Remove `set arch riscv:rv%d`
Tim Newsome
1
-1
/
+0
2017-12-20
Verify that F18 does not exist on FPU-less targets
Tim Newsome
1
-17
/
+20
2017-12-12
Display env variables used when invoking OpenOCD
Tim Newsome
1
-1
/
+6
2017-12-01
Ensure there are no unnamed registers.
Tim Newsome
1
-0
/
+2
2017-11-30
Clean up VcsSim init()
Tim Newsome
1
-2
/
+12
2017-11-27
Rename sbadaddr to satp
Andrew Waterman
1
-3
/
+3
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