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debug
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gdbserver.py
Age
Commit message (
Expand
)
Author
Files
Lines
2019-07-26
Make newer version of pylint happy.
misc
Tim Newsome
1
-7
/
+7
2019-07-26
Let the debugger enable mstatus.F if necessary.
Tim Newsome
1
-1
/
+0
2019-06-14
Work better with mainline gdb (#192)
Tim Newsome
1
-8
/
+8
2019-04-04
Test simultaneous resume using hasel. (#186)
Tim Newsome
1
-8
/
+13
2019-03-11
Add SmpSimultaneousRunHalt test. (#181)
Tim Newsome
1
-0
/
+49
2019-02-14
Test `-rtos hwthread` (#178)
Tim Newsome
1
-10
/
+12
2019-01-07
Fail on unsupported SREC type.
Tim Newsome
1
-0
/
+2
2018-12-31
Fix MemTestBlock
Tim Newsome
1
-20
/
+41
2018-12-03
Reduce download size a bit.
Tim Newsome
1
-4
/
+8
2018-11-30
Use more than 1KB for download test.
Tim Newsome
1
-1
/
+1
2018-11-16
Make pylint happy.
Tim Newsome
1
-3
/
+6
2018-11-14
Merge pull request #165 from riscv/flash
Tim Newsome
1
-13
/
+33
2018-11-14
Cleanup and renamed test flag to invalid_memory_returns_zero
cgsfv
1
-2
/
+2
2018-11-13
Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fix
cgsfv
1
-0
/
+52
2018-10-31
Fix remaining tests to work from flash:
Tim Newsome
1
-4
/
+12
2018-10-29
Almost all tests pass with HiFive1-flash
Tim Newsome
1
-3
/
+12
2018-10-29
Tweak debug tests to run out of flash.
Tim Newsome
1
-6
/
+9
2018-10-24
Merge branch 'TriggerLoadAddressInstant'
Tim Newsome
1
-12
/
+1
2018-10-24
Re-enable TriggerStoreAddressInstant
Tim Newsome
1
-12
/
+1
2018-10-05
Make HwWatchpoint test fail on incorrect result.
hw_watchpoint
Tim Newsome
1
-5
/
+8
2018-10-03
Added tests for hw and sw watchpoints
cgsfv
1
-0
/
+56
2018-09-03
Merge pull request #156 from riscv/PrivChange
Tim Newsome
1
-27
/
+26
2018-08-31
Fix CustomRegisterTest.
Tim Newsome
1
-1
/
+2
2018-08-29
Add test case for `riscv expose_custom`.
Tim Newsome
1
-0
/
+30
2018-08-28
Reset address translation/perms before PrivChange
Tim Newsome
1
-27
/
+26
2018-08-27
Neuter TriggerStoreAddressInstant
Tim Newsome
1
-1
/
+13
2018-08-27
Make pylint happy.
Tim Newsome
1
-1
/
+2
2018-08-25
Temporarily disabling PrivChange test
Andrew Waterman
1
-22
/
+23
2018-08-23
Make pylint happy with change d1d2d953b5016b465.
Tim Newsome
1
-2
/
+3
2018-08-23
Merge pull request #153 from dmitryryzhov/rtos-switch-active-thread
Tim Newsome
1
-0
/
+28
2018-08-22
Disable MulticoreRunHaltStepiTest
Tim Newsome
1
-52
/
+52
2018-08-22
Add debug test, which checks that openocd correctly switch active thread on a...
Dmitry Ryzhov
1
-0
/
+28
2018-08-13
Add jump/hbreak test.
Tim Newsome
1
-0
/
+23
2018-07-03
rwatch/watch on explicit address
Tim Newsome
1
-2
/
+4
2018-05-18
Fix MulticoreRunHaltStepiTest
Tim Newsome
1
-19
/
+37
2018-05-14
Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-single
Megan Wachs
1
-17
/
+4
2018-05-14
Make DownloadTest properly park other harts.
Tim Newsome
1
-1
/
+2
2018-05-14
debug: remove some unintentionally added newlines
Megan Wachs
1
-2
/
+0
2018-05-14
debug: Fixing the non-RTOS behavior for DownloadTest
Megan Wachs
1
-7
/
+16
2018-05-11
debug: mark more tests as single-hart tests
Megan Wachs
1
-6
/
+13
2018-04-30
Fix formatting to make pylint happy.
Tim Newsome
1
-5
/
+6
2018-04-27
debug: need to clear satp before changing priv
debug-clear-satp
Megan Wachs
1
-0
/
+7
2018-04-09
Compute gdb command timeout based on ops estimate
Tim Newsome
1
-1
/
+1
2018-03-01
Ensure an error when reading a non-existent CSR.
Tim Newsome
1
-0
/
+13
2018-02-09
Test resuming from a trigger.
resume_from_trigger
Tim Newsome
1
-0
/
+5
2018-01-08
Deal with gdb reporting pmpcfg0 not existing.
Tim Newsome
1
-3
/
+7
2018-01-05
Add test for multicore failure
Tim Newsome
1
-0
/
+28
2017-12-27
Test FPRs that aren't XLEN in size.
Tim Newsome
1
-0
/
+6
2017-12-20
Verify that F18 does not exist on FPU-less targets
Tim Newsome
1
-17
/
+20
2017-12-01
Ensure there are no unnamed registers.
Tim Newsome
1
-0
/
+2
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