Age | Commit message (Collapse) | Author | Files | Lines |
|
We were using a variety of deprecated commands.
The driving force behind this was the new way to use `expr{}` as the old
way no longer works with mainline OpenOCD.
|
|
|
|
Include Zicntr in Spike ISA string
|
|
Add more tests for amo[max/maxu/min/minu]_w
|
|
Spike no longer enables Zicntr by default, so turn it on explicitly.
cc @jerryz123
|
|
|
|
|
|
|
|
|
|
Fix intermittent IcountTest failure on multi hart.
|
|
Don't build with -DMULTICORE because this is not a test that really does
multicore. It's one where we just want to park the other harts.
|
|
debug: fix pylint error W0621 redefined-outer-name
|
|
Add test for icount triggers.
|
|
|
|
|
|
|
|
Fix EtriggerTest on multi-hart targets.
|
|
The trap handler for norvc systems has an incorrect jump offset
Signed-off-by: Yujia Qiao <code@rapiz.me>
|
|
Related to issue https://github.com/riscv-software-src/riscv-tests/issues/453
It seems to be the only modification needed there.
It may break backward compatibility with (very?) old compilers.
Signed-off-by: Pascal Cotret <pascal.cotret@gmail.com>
|
|
env has been updated with trap and page fault filtering mechanism.
Such filtering allows tests to be written in such a way so that
exceptions/traps can be filtered by test case author and negative tests
can be written.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
|
|
Need to set the etrigger on the hart we're running the test against.
|
|
|
|
...because the ma_data test requires this feature.
Don't merge until https://github.com/riscv-software-src/riscv-isa-sim/pull/1206 is merged.
|
|
debug: Add Itrigger test.
|
|
|
|
|
|
debug: Add etrigger test.
|
|
|
|
|
|
|
|
The list of active tests in isa/ depends, via the COMPILER_SUPPORTS_*
macros, on running the RISC-V compiler, so pass the necessary options
when invoking make clean there.
|
|
Add CeaseStepiTest and CeaseRunTest
|
|
Test that we work correctly when the hart we're debugging ceases to
respond while it's running.
|
|
Test that we work correctly when the hart we're debugging ceases to
respond during stepi.
Add wait parameter to Gdb.stepi(), in case stepi isn't expected to complete.
Parse "could not read registers" error from gdb
|
|
Confirm basic debug still works when other harts have been parked using
a `cease` instruction. Check that the unavailable harts are inaccessible
from gdb.
Add Gdb.expect()
Parse "unknown thread" error from gdb.
|
|
Also make the semi-hosting test program return 10. That's more fragile
than returning 0, so makes for a better test.
|
|
|
|
It is allowed that M-mode only implementation could skip cycle/instret
if the Zicntr is not included.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
|
|
This gives you less noise in the log, and more chance of figuring out
what code was actually executed.
|
|
`flush regs` is being deprecated.
|
|
`cease` is not a standard RISC-V extension, but is (was?) implemented in
Rocket, and also exists in some SiFive cores. It's useful to test
OpenOCD behavior when a hart becomes unavailable.
See also https://github.com/chipsalliance/rocket-chip/issues/1868
|
|
|
|
Also change the test itself to require less RAM than it did previously.
(It had required more than 32KB.)
|
|
It would fail intermittently. We can't guarantee all harts resume
simultaneously. When we let multiple harts run to a breakpoint at the
end of the same loop, one is likely to get there first, and the second
won't make it.
To avoid this problem, run for a short amount of time instead of to a
breakpoint.
|
|
Before it might fail incorrectly, because main was close to trap_entry.
|
|
* Specify trigger type=2 in trigger.S
Previous tests implicitly assume triggers only support type=2. However,
a trigger may support multiple types, i.e., type=15. This commit
explicitly specifies type=2 in trigger.S to support type 15.
* Update debug/programs/trigger.S
Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
Co-authored-by: Tim Newsome <tim@sifive.com>
|
|
Between October 13 and October 19, something happened that makes the
multi-spike tests 4 times slower. Rolling back spike, OpenOCD, or
riscv-tests doesn't affect this. Presumably it's due to a kernel or
python change in my Ubuntu system.
I don't have time to look at this right now, so just increase the timeouts. :-(
If I had to guess, there could be a bug in rbb_daisychain.py that wastes
a lot of time.
|
|
https://github.com/riscv-software-src/riscv-isa-sim/pull/889 put a UART
at the address we were using in our 32-bit debug tests.
|
|
Fix long line to make pylint happy.
|
|
Get coverage of progbuf FPR accesses.
|