diff options
Diffstat (limited to 'isa/rv32uzba')
| -rw-r--r-- | isa/rv32uzba/Makefrag | 14 | ||||
| -rw-r--r-- | isa/rv32uzba/sh1add.S | 85 | ||||
| -rw-r--r-- | isa/rv32uzba/sh2add.S | 85 | ||||
| -rw-r--r-- | isa/rv32uzba/sh3add.S | 85 |
4 files changed, 269 insertions, 0 deletions
diff --git a/isa/rv32uzba/Makefrag b/isa/rv32uzba/Makefrag new file mode 100644 index 0000000..39a2c99 --- /dev/null +++ b/isa/rv32uzba/Makefrag @@ -0,0 +1,14 @@ +#======================================================================= +# Makefrag for rv32uzba tests +#----------------------------------------------------------------------- + +rv32uzba_sc_tests = \ + sh1add \ + sh2add \ + sh3add \ + +rv32uzba_p_tests = $(addprefix rv32uzba-p-, $(rv32uzba_sc_tests)) +rv32uzba_v_tests = $(addprefix rv32uzba-v-, $(rv32uzba_sc_tests)) +rv32uzba_ps_tests = $(addprefix rv32uzba-ps-, $(rv32uzba_sc_tests)) + +spike_tests += $(rv32uzba_p_tests) $(rv32uzba_v_tests) diff --git a/isa/rv32uzba/sh1add.S b/isa/rv32uzba/sh1add.S new file mode 100644 index 0000000..03ae190 --- /dev/null +++ b/isa/rv32uzba/sh1add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh1add.S +#----------------------------------------------------------------------------- +# +# Test sh1add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh1add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh1add, 0x00000003, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh1add, 0x0000000d, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh1add, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, sh1add, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, sh1add, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 8, sh1add, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 9, sh1add, 0xfffffffe, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 10, sh1add, 0x00007ffd, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 11, sh1add, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 12, sh1add, 0xffff7ffe, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 13, sh1add, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 14, sh1add, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 15, sh1add, 0xfffffffd, 0xffffffff, 0xffffffff ); + + TEST_RR_OP( 16, sh1add, 0x80000001, 0x00000001, 0x7fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh1add, 37, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh1add, 39, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh1add, 37, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh1add, 39, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh1add, 41, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add, 41, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add, 41, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add, 41, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add, 41, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh1add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh1add, 64, 32 ); + TEST_RR_ZEROSRC12( 37, sh1add, 0 ); + TEST_RR_ZERODEST( 38, sh1add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzba/sh2add.S b/isa/rv32uzba/sh2add.S new file mode 100644 index 0000000..057dba5 --- /dev/null +++ b/isa/rv32uzba/sh2add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh2add.S +#----------------------------------------------------------------------------- +# +# Test sh2add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh2add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh2add, 0x00000005, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh2add, 0x00000013, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh2add, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, sh2add, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, sh2add, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 8, sh2add, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 9, sh2add, 0xfffffffc, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 10, sh2add, 0x00007ffb, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 11, sh2add, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 12, sh2add, 0xffff7ffc, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 13, sh2add, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 14, sh2add, 0xfffffffd, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 15, sh2add, 0xfffffffb, 0xffffffff, 0xffffffff ); + + TEST_RR_OP( 16, sh2add, 0x80000003, 0x00000001, 0x7fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh2add, 63, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh2add, 65, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh2add, 63, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh2add, 67, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh2add, 71, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add, 71, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add, 71, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add, 71, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add, 71, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh2add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh2add, 128, 32 ); + TEST_RR_ZEROSRC12( 37, sh2add, 0 ); + TEST_RR_ZERODEST( 38, sh2add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzba/sh3add.S b/isa/rv32uzba/sh3add.S new file mode 100644 index 0000000..530241e --- /dev/null +++ b/isa/rv32uzba/sh3add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh3add.S +#----------------------------------------------------------------------------- +# +# Test sh3add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh3add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh3add, 0x00000009, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh3add, 0x0000001f, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh3add, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, sh3add, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, sh3add, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 8, sh3add, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 9, sh3add, 0xfffffff8, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 10, sh3add, 0x00007ff7, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 11, sh3add, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 12, sh3add, 0xffff7ff8, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 13, sh3add, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 14, sh3add, 0xfffffff9, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 15, sh3add, 0xfffffff7, 0xffffffff, 0xffffffff ); + + TEST_RR_OP( 16, sh3add, 0x80000007, 0x00000001, 0x7fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh3add, 115, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh3add, 117, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh3add, 115, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh3add, 123, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh3add, 131, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add, 131, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add, 131, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add, 131, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add, 131, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh3add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh3add, 256, 32 ); + TEST_RR_ZEROSRC12( 37, sh3add, 0 ); + TEST_RR_ZERODEST( 38, sh3add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END |