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| author | Andrew Waterman <andrew@sifive.com> | 2017-08-04 10:20:00 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-08-04 10:20:00 -0700 |
| commit | c26d7f39e6fabde07f16fd35d67a2414e674d488 (patch) | |
| tree | f5303afe9d432c612c082007b755723a76704f86 /isa | |
| parent | 7ab7ad44e66ba9bc2d91e04773efa4f87a1d8a3b (diff) | |
| download | riscv-tests-c26d7f39e6fabde07f16fd35d67a2414e674d488.zip riscv-tests-c26d7f39e6fabde07f16fd35d67a2414e674d488.tar.gz riscv-tests-c26d7f39e6fabde07f16fd35d67a2414e674d488.tar.bz2 | |
RV32 div tests should use -2^31 for min value, not -2^63
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv32um/div.S | 6 | ||||
| -rw-r--r-- | isa/rv32um/rem.S | 6 | ||||
| -rw-r--r-- | isa/rv32um/remu.S | 6 |
3 files changed, 9 insertions, 9 deletions
diff --git a/isa/rv32um/div.S b/isa/rv32um/div.S index a4504a7..24dc9ff 100644 --- a/isa/rv32um/div.S +++ b/isa/rv32um/div.S @@ -22,10 +22,10 @@ RVTEST_CODE_BEGIN TEST_RR_OP( 4, div, -3, 20, -6 ); TEST_RR_OP( 5, div, 3, -20, -6 ); - TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 ); - TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 ); + TEST_RR_OP( 6, div, -1<<31, -1<<31, 1 ); + TEST_RR_OP( 7, div, -1<<31, -1<<31, -1 ); - TEST_RR_OP( 8, div, -1, -1<<63, 0 ); + TEST_RR_OP( 8, div, -1, -1<<31, 0 ); TEST_RR_OP( 9, div, -1, 1, 0 ); TEST_RR_OP(10, div, -1, 0, 0 ); diff --git a/isa/rv32um/rem.S b/isa/rv32um/rem.S index c318e2c..7955736 100644 --- a/isa/rv32um/rem.S +++ b/isa/rv32um/rem.S @@ -22,10 +22,10 @@ RVTEST_CODE_BEGIN TEST_RR_OP( 4, rem, 2, 20, -6 ); TEST_RR_OP( 5, rem, -2, -20, -6 ); - TEST_RR_OP( 6, rem, 0, -1<<63, 1 ); - TEST_RR_OP( 7, rem, 0, -1<<63, -1 ); + TEST_RR_OP( 6, rem, 0, -1<<31, 1 ); + TEST_RR_OP( 7, rem, 0, -1<<31, -1 ); - TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 8, rem, -1<<31, -1<<31, 0 ); TEST_RR_OP( 9, rem, 1, 1, 0 ); TEST_RR_OP(10, rem, 0, 0, 0 ); diff --git a/isa/rv32um/remu.S b/isa/rv32um/remu.S index 38d641d..a96cfc1 100644 --- a/isa/rv32um/remu.S +++ b/isa/rv32um/remu.S @@ -22,10 +22,10 @@ RVTEST_CODE_BEGIN TEST_RR_OP( 4, remu, 20, 20, -6 ); TEST_RR_OP( 5, remu, -20, -20, -6 ); - TEST_RR_OP( 6, remu, 0, -1<<63, 1 ); - TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 ); + TEST_RR_OP( 6, remu, 0, -1<<31, 1 ); + TEST_RR_OP( 7, remu, -1<<31, -1<<31, -1 ); - TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 8, remu, -1<<31, -1<<31, 0 ); TEST_RR_OP( 9, remu, 1, 1, 0 ); TEST_RR_OP(10, remu, 0, 0, 0 ); |