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:
riscv-tools/riscv-tests.git
attempt-travis-fix
ceasetest2
compliance_tests
cs152-sp18-lab3
debug
debug-0.13
debug-clear-satp
debug-delete-sim
debug_auth
debug_disassemble
disable_unavailable
dma-memcpy
eos20-bringup
hw_watchpoint
interrupts
master
misc
no_progbuf
priv
privchange-dontdeleteme
python3
rekall
resume_from_trigger
riscv-tests-sail
rtos
rvt-master
smi-demo
split-isa-tests
sqrt-171
tmp
trap_entry_align
trap_entry_align-1
travis-dev
trigger_priority
usb_error
xlen_fix
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Commit message
Author
Age
ceasetest2
Check basic debugging still works in CeaseMulti
Tim Newsome
19 months
debug
Add debug statement.
Tim Newsome
4 years
debug_disassemble
debug: On failure, disassemble close instructions.
Tim Newsome
21 months
disable_unavailable
debug: Disable Unavailable tests.
Tim Newsome
8 months
master
Change DTM IDCODE from SiFive HiFive1's 0x10e31913 to Spike's 0xdeadbeef (#565)
Tommy Murphy
3 days
misc
Make newer version of pylint happy.
Tim Newsome
5 years
python3
Move to Python 3.
Tim Newsome
5 years
riscv-tests-sail
removed the env/ directory, which was a submodule dir. replaced at a higher l...
William McSpaddden
4 weeks
tmp
tmp
Andrew Waterman
4 years
trigger_priority
Remove ineffective tests.
Tim Newsome
2 years
[...]
Age
Commit message
Author
Files
Lines
2020-01-08
tmp
tmp
Andrew Waterman
1
-20
/
+0
2019-12-24
submodule: bump env version (#229)
Chih-Min Chao
1
-5
/
+10
2019-12-18
Hardcode misa values for all spike targets. (#227)
Tim Newsome
9
-7
/
+27
2019-12-18
Tell people where to get software. (#226)
Tim Newsome
1
-3
/
+9
2019-12-10
benchmarks: Simplify TLS initialisation (#224)
James Clarke
3
-19
/
+5
2019-12-10
Improve parallellism in debug test Makefile (#223)
Tim Newsome
2
-15
/
+28
2019-12-02
Use a small binary to set up HiFive Unleashed. (#221)
Tim Newsome
3
-10
/
+10
2019-11-22
Move to Python 3. (#218)
Tim Newsome
4
-75
/
+78
2019-11-04
Remove cruft from icache-alias test
Andrew Waterman
1
-35
/
+0
2019-11-04
Add rv64si-p-icache-alias
Andrew Waterman
2
-0
/
+177
[...]