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| author | Andrew Waterman <andrew@sifive.com> | 2017-05-05 16:28:06 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-05-05 16:28:06 -0700 |
| commit | bb8f7775294e612a8ba91d65d5097b19cb00394a (patch) | |
| tree | 3f0bb9d635675f9d5526ca8d14231580b0c4f42c /isa | |
| parent | aec2a5b9dd4cb10b40a1c37d531ed4b8712227d1 (diff) | |
| download | riscv-tests-bb8f7775294e612a8ba91d65d5097b19cb00394a.zip riscv-tests-bb8f7775294e612a8ba91d65d5097b19cb00394a.tar.gz riscv-tests-bb8f7775294e612a8ba91d65d5097b19cb00394a.tar.bz2 | |
Check UXL in sstatus
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64si/csr.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S index 13dbf26..0576678 100644 --- a/isa/rv64si/csr.S +++ b/isa/rv64si/csr.S @@ -24,6 +24,11 @@ RVTEST_CODE_BEGIN #define SSTATUS_SPP MSTATUS_MPP #endif + # For RV64, make sure UXL encodes RV64. (UXL does not exist for RV32.) +#if __riscv_xlen == 64 + TEST_CASE(13, a0, SSTATUS_UXL & (SSTATUS_UXL << 1), csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1) +#endif + csrwi sscratch, 3 TEST_CASE( 2, a0, 3, csrr a0, sscratch); TEST_CASE( 3, a1, 3, csrrci a1, sscratch, 1); |