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authorAndrew Waterman <andrew@sifive.com>2017-05-05 14:40:01 -0700
committerAndrew Waterman <andrew@sifive.com>2017-05-05 14:40:01 -0700
commitaec2a5b9dd4cb10b40a1c37d531ed4b8712227d1 (patch)
tree613bb8d2fc672413cd94806ee4f59c6f56177099 /isa
parentb831fe7f4723ae745c4c31ca0bc628277dba94ef (diff)
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Test that superpage PTEs trap when PPN LSBs are set
Diffstat (limited to 'isa')
-rw-r--r--isa/rv64si/dirty.S18
1 files changed, 18 insertions, 0 deletions
diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S
index 50bdcfb..783522c 100644
--- a/isa/rv64si/dirty.S
+++ b/isa/rv64si/dirty.S
@@ -55,6 +55,19 @@ RVTEST_CODE_BEGIN
li a0, PTE_A | PTE_D
and t0, t0, a0
bne t0, a0, die
+
+ # Enter MPRV again
+ li t0, MSTATUS_MPRV
+ csrs mstatus, t0
+
+ # Make sure that superpage entries trap when PPN LSBs are set.
+ li TESTNUM, 4
+ lw a0, page_table_1 - DRAM_BASE
+ or a0, a0, 1 << PTE_PPN_SHIFT
+ sw a0, page_table_1 - DRAM_BASE, t0
+ sfence.vma
+ sw a0, page_table_1 - DRAM_BASE, t0
+ j die
RVTEST_PASS
@@ -93,6 +106,11 @@ skip:
mret
1:
+ li t1, 4
+ bne TESTNUM, t1, 1f
+ j pass
+
+1:
die:
RVTEST_FAIL