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| author | Andrew Waterman <aswaterman@gmail.com> | 2018-01-02 21:13:38 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-01-02 21:13:38 -0800 |
| commit | 03447f08863f1f25243c52a2139d0c968157a9f8 (patch) | |
| tree | 91b24fd1be5a3999dc212391f45e1f27b89e13aa /isa | |
| parent | d359b6252eceb5e28f1048591750954d09efd12b (diff) | |
| download | riscv-tests-03447f08863f1f25243c52a2139d0c968157a9f8.zip riscv-tests-03447f08863f1f25243c52a2139d0c968157a9f8.tar.gz riscv-tests-03447f08863f1f25243c52a2139d0c968157a9f8.tar.bz2 | |
Test access exception behavior for illegal addresses (#111)
OK'd by @palmer-dabbelt
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64mi/Makefrag | 1 | ||||
| -rw-r--r-- | isa/rv64mi/access.S | 70 |
2 files changed, 71 insertions, 0 deletions
diff --git a/isa/rv64mi/Makefrag b/isa/rv64mi/Makefrag index fb38e5f..c81c24e 100644 --- a/isa/rv64mi/Makefrag +++ b/isa/rv64mi/Makefrag @@ -3,6 +3,7 @@ #----------------------------------------------------------------------- rv64mi_sc_tests = \ + access \ breakpoint \ csr \ mcsr \ diff --git a/isa/rv64mi/access.S b/isa/rv64mi/access.S new file mode 100644 index 0000000..202a364 --- /dev/null +++ b/isa/rv64mi/access.S @@ -0,0 +1,70 @@ +# See LICENSE for license details. + +#***************************************************************************** +# access.S +#----------------------------------------------------------------------------- +# +# Test access-exception behavior. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + .align 2 + + # Flipping just the MSB should result in an illegal address for RV64. + la t2, fail + li t0, 1 << (__riscv_xlen - 1) + xor t0, t0, t2 + + # jalr to an illegal address should commit (hence should write rd). + # after the pc is set to rs1, an access exception should be raised. + li TESTNUM, 2 + li t1, CAUSE_FETCH_ACCESS + la t3, 1f + li t2, 0 + jalr t2, t0 +1: + + # A load to an illegal address should not commit. + li TESTNUM, 3 + li t1, CAUSE_LOAD_ACCESS + la t3, 1f + mv t2, t3 + lb t2, (t0) + j fail +1: + + j pass + + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + li a0, 2 + beq TESTNUM, a0, 2f + li a0, 3 + beq TESTNUM, a0, 2f + j fail + +2: + bne t2, t3, fail + + csrr t2, mcause + bne t2, t1, fail + + csrw mepc, t3 + mret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END |