Merge commit '3dc00e7' into smi-demosmi-demo

93 files changed, 830 insertions, 476 deletions

diff --git a/isa/Makefile b/isa/Makefile
index 636cbbe..4e1af6c 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -5,10 +5,15 @@
 src_dir := .
 
 include $(src_dir)/rv64ui/Makefrag
+include $(src_dir)/rv64um/Makefrag
+include $(src_dir)/rv64ua/Makefrag
 include $(src_dir)/rv64uf/Makefrag
+include $(src_dir)/rv64ud/Makefrag
 include $(src_dir)/rv64si/Makefrag
 include $(src_dir)/rv64mi/Makefrag
 include $(src_dir)/rv32ui/Makefrag
+include $(src_dir)/rv32um/Makefrag
+include $(src_dir)/rv32ua/Makefrag
 include $(src_dir)/rv32si/Makefrag
 include $(src_dir)/rv32mi/Makefrag
 
@@ -61,11 +66,16 @@ tests += $$($(1)_tests)
 endef
 
 $(eval $(call compile_template,rv32ui,-m32))
+$(eval $(call compile_template,rv32um,-m32))
+$(eval $(call compile_template,rv32ua,-m32))
 $(eval $(call compile_template,rv32si,-m32))
 $(eval $(call compile_template,rv32mi,-m32))
 ifeq ($(XLEN),64)
 $(eval $(call compile_template,rv64ui))
+$(eval $(call compile_template,rv64um))
+$(eval $(call compile_template,rv64ua))
 $(eval $(call compile_template,rv64uf))
+$(eval $(call compile_template,rv64ud))
 $(eval $(call compile_template,rv64si))
 $(eval $(call compile_template,rv64mi))
 endif
diff --git a/isa/rv32mi/Makefrag b/isa/rv32mi/Makefrag
index 9aeb12d..c8fbcf4 100644
--- a/isa/rv32mi/Makefrag
+++ b/isa/rv32mi/Makefrag
@@ -12,7 +12,6 @@ rv32mi_sc_tests = \
 	scall \
 	sbreak \
 	shamt \
-	wfi \
 
 rv32mi_mc_tests = \
 	ipi \
diff --git a/isa/rv32mi/wfi.S b/isa/rv32mi/wfi.S
deleted file mode 100644
index d5cb3cb..0000000
--- a/isa/rv32mi/wfi.S
+++ /dev/null
@@ -1,8 +0,0 @@
-# See LICENSE for license details.
-
-#include "riscv_test.h"
-#undef RVTEST_RV64S
-#define RVTEST_RV64S RVTEST_RV32M
-#define __MACHINE_MODE
-
-#include "../rv64si/wfi.S"
diff --git a/isa/rv32ua/Makefrag b/isa/rv32ua/Makefrag
new file mode 100644
index 0000000..575dc6a
--- /dev/null
+++ b/isa/rv32ua/Makefrag
@@ -0,0 +1,12 @@
+#=======================================================================
+# Makefrag for rv32ua tests
+#-----------------------------------------------------------------------
+
+rv32ua_sc_tests = \
+	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
+	lrsc \
+
+rv32ua_p_tests = $(addprefix rv32ua-p-, $(rv32ua_sc_tests))
+rv32ua_v_tests = $(addprefix rv32ua-v-, $(rv32ua_sc_tests))
+
+spike32_tests += $(rv32ua_p_tests) $(rv32ua_v_tests)
diff --git a/isa/rv32ui/amoadd_w.S b/isa/rv32ua/amoadd_w.S
index 975ae1d..975ae1d 100644
--- a/isa/rv32ui/amoadd_w.S
+++ b/isa/rv32ua/amoadd_w.S
diff --git a/isa/rv32ui/amoand_w.S b/isa/rv32ua/amoand_w.S
index 7c989c2..7c989c2 100644
--- a/isa/rv32ui/amoand_w.S
+++ b/isa/rv32ua/amoand_w.S
diff --git a/isa/rv32ui/amomax_w.S b/isa/rv32ua/amomax_w.S
index 698cf26..698cf26 100644
--- a/isa/rv32ui/amomax_w.S
+++ b/isa/rv32ua/amomax_w.S
diff --git a/isa/rv32ui/amomaxu_w.S b/isa/rv32ua/amomaxu_w.S
index 27c4ddf..27c4ddf 100644
--- a/isa/rv32ui/amomaxu_w.S
+++ b/isa/rv32ua/amomaxu_w.S
diff --git a/isa/rv32ui/amomin_w.S b/isa/rv32ua/amomin_w.S
index a6a0947..a6a0947 100644
--- a/isa/rv32ui/amomin_w.S
+++ b/isa/rv32ua/amomin_w.S
diff --git a/isa/rv32ui/amominu_w.S b/isa/rv32ua/amominu_w.S
index ce06e1c..ce06e1c 100644
--- a/isa/rv32ui/amominu_w.S
+++ b/isa/rv32ua/amominu_w.S
diff --git a/isa/rv32ui/amoor_w.S b/isa/rv32ua/amoor_w.S
index 0988c66..0988c66 100644
--- a/isa/rv32ui/amoor_w.S
+++ b/isa/rv32ua/amoor_w.S
diff --git a/isa/rv32ui/amoswap_w.S b/isa/rv32ua/amoswap_w.S
index a32ae74..a32ae74 100644
--- a/isa/rv32ui/amoswap_w.S
+++ b/isa/rv32ua/amoswap_w.S
diff --git a/isa/rv32ui/amoxor_w.S b/isa/rv32ua/amoxor_w.S
index d4b775f..d4b775f 100644
--- a/isa/rv32ui/amoxor_w.S
+++ b/isa/rv32ua/amoxor_w.S
diff --git a/isa/rv32ui/lrsc.S b/isa/rv32ua/lrsc.S
index 3a3d05a..3a3d05a 100644
--- a/isa/rv32ui/lrsc.S
+++ b/isa/rv32ua/lrsc.S
diff --git a/isa/rv32ui/Makefrag b/isa/rv32ui/Makefrag
index 4bdebb5..6cb6c08 100644
--- a/isa/rv32ui/Makefrag
+++ b/isa/rv32ui/Makefrag
@@ -5,19 +5,14 @@
 rv32ui_sc_tests = \
 	simple \
 	add addi \
-	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
-	lrsc \
 	and andi \
 	auipc \
 	beq bge bgeu blt bltu bne \
-	div divu \
 	fence_i \
 	j jal jalr \
 	lb lbu lh lhu lw \
 	lui \
-	mul mulh mulhu mulhsu \
 	or ori \
-	rem remu \
 	sb sh sw \
 	sll slli \
 	slt slti \
diff --git a/isa/rv32ui/divuw.S b/isa/rv32ui/divuw.S
deleted file mode 100644
index 0868eeb..0000000
--- a/isa/rv32ui/divuw.S
+++ /dev/null
@@ -1,41 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# divuw.S
-#-----------------------------------------------------------------------------
-#
-# Test divuw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
-  #-------------------------------------------------------------
-  # Arithmetic tests
-  #-------------------------------------------------------------
-
-  TEST_RR_OP( 2, divuw,         3,  20,   6 );
-  TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32,   6 );
-  TEST_RR_OP( 4, divuw,         0,  20,  -6 );
-  TEST_RR_OP( 5, divuw,         0, -20,  -6 );
-
-  TEST_RR_OP( 6, divuw, -1<<31, -1<<31,  1 );
-  TEST_RR_OP( 7, divuw, 0,      -1<<31, -1 );
-
-  TEST_RR_OP( 8, divuw, -1, -1<<31, 0 );
-  TEST_RR_OP( 9, divuw, -1,      1, 0 );
-  TEST_RR_OP(10, divuw, -1,      0, 0 );
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
diff --git a/isa/rv32ui/divw.S b/isa/rv32ui/divw.S
deleted file mode 100644
index 4d91749..0000000
--- a/isa/rv32ui/divw.S
+++ /dev/null
@@ -1,41 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# divw.S
-#-----------------------------------------------------------------------------
-#
-# Test divw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
-  #-------------------------------------------------------------
-  # Arithmetic tests
-  #-------------------------------------------------------------
-
-  TEST_RR_OP( 2, divw,  3,  20,   6 );
-  TEST_RR_OP( 3, divw, -3, -20,   6 );
-  TEST_RR_OP( 4, divw, -3,  20,  -6 );
-  TEST_RR_OP( 5, divw,  3, -20,  -6 );
-
-  TEST_RR_OP( 6, divw, -1<<31, -1<<31,  1 );
-  TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 );
-
-  TEST_RR_OP( 8, divw, -1, -1<<31, 0 );
-  TEST_RR_OP( 9, divw, -1,      1, 0 );
-  TEST_RR_OP(10, divw, -1,      0, 0 );
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
diff --git a/isa/rv32ui/mulw.S b/isa/rv32ui/mulw.S
deleted file mode 100644
index 577c93e..0000000
--- a/isa/rv32ui/mulw.S
+++ /dev/null
@@ -1,72 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# mulw.S
-#-----------------------------------------------------------------------------
-#
-# Test mulw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
-  #-------------------------------------------------------------
-  # Arithmetic tests
-  #-------------------------------------------------------------
-
-  TEST_RR_OP( 2,  mulw, 0x00000000, 0x00000000, 0x00000000 );
-  TEST_RR_OP( 3,  mulw, 0x00000001, 0x00000001, 0x00000001 );
-  TEST_RR_OP( 4,  mulw, 0x00000015, 0x00000003, 0x00000007 );
-
-  TEST_RR_OP( 5,  mulw, 0x00000000, 0x00000000, 0xffff8000 );
-  TEST_RR_OP( 6,  mulw, 0x00000000, 0x80000000, 0x00000000 );
-  TEST_RR_OP( 7,  mulw, 0x00000000, 0x80000000, 0xffff8000 );
-
-  #-------------------------------------------------------------
-  # Source/Destination tests
-  #-------------------------------------------------------------
-
-  TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 );
-  TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 );
-  TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 );
-
-  #-------------------------------------------------------------
-  # Bypassing tests
-  #-------------------------------------------------------------
-
-  TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 );
-  TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 );
-  TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 );
-
-  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 );
-  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 );
-  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 );
-  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 );
-  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 );
-  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 );
-
-  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 );
-  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 );
-  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 );
-  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 );
-  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 );
-  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 );
-
-  TEST_RR_ZEROSRC1( 26, mulw, 0, 31 );
-  TEST_RR_ZEROSRC2( 27, mulw, 0, 32 );
-  TEST_RR_ZEROSRC12( 28, mulw, 0 );
-  TEST_RR_ZERODEST( 29, mulw, 33, 34 );
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
diff --git a/isa/rv32ui/sh.S b/isa/rv32ui/sh.S
index 387e181..6c47274 100644
--- a/isa/rv32ui/sh.S
+++ b/isa/rv32ui/sh.S
@@ -68,6 +68,23 @@ RVTEST_CODE_BEGIN
   TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat );
   TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat );
 
+  #---------------------------------------------------------------
+  # Side effect tests
+  #---------------------------------------------------------------
+
+  # sh to a word aligned address should only affect the 2 lower bytes
+  # and should leave the 2 upper bytes unmodified.
+  #
+  # In this test we write 2 bytes to the lower 2 bytes of the word
+  # tdat11 and then ensure that the both the upper 2 bytes and
+  # lower 2 bytes are as expected.
+  TEST_CASE( 24, x3, 0x12343098, \
+    la  x1, tdat11; \
+    li  x2, 0x00003098; \
+    sh x2, 0(x1); \
+    lw x3, 0(x1); \
+  )
+
   li a0, 0xbeef
   la a1, tdat
   sh a0, 6(a1)
@@ -92,5 +109,6 @@ tdat7:  .half 0xbeef
 tdat8:  .half 0xbeef
 tdat9:  .half 0xbeef
 tdat10: .half 0xbeef
+tdat11: .word 0x12345678
 
 RVTEST_DATA_END
diff --git a/isa/rv32um/Makefrag b/isa/rv32um/Makefrag
new file mode 100644
index 0000000..1391c6a
--- /dev/null
+++ b/isa/rv32um/Makefrag
@@ -0,0 +1,13 @@
+#=======================================================================
+# Makefrag for rv32um tests
+#-----------------------------------------------------------------------
+
+rv32um_sc_tests = \
+	div divu \
+	mul mulh mulhsu mulhu \
+	rem remu \
+
+rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sc_tests))
+rv32um_v_tests = $(addprefix rv32um-v-, $(rv32um_sc_tests))
+
+spike32_tests += $(rv32um_p_tests) $(rv32um_v_tests)
diff --git a/isa/rv32ui/div.S b/isa/rv32um/div.S
index a4504a7..a4504a7 100644
--- a/isa/rv32ui/div.S
+++ b/isa/rv32um/div.S
diff --git a/isa/rv32ui/divu.S b/isa/rv32um/divu.S
index cd348c9..cd348c9 100644
--- a/isa/rv32ui/divu.S
+++ b/isa/rv32um/divu.S
diff --git a/isa/rv32ui/mul.S b/isa/rv32um/mul.S
index 0368629..0368629 100644
--- a/isa/rv32ui/mul.S
+++ b/isa/rv32um/mul.S
diff --git a/isa/rv32ui/mulh.S b/isa/rv32um/mulh.S
index e583f5f..e583f5f 100644
--- a/isa/rv32ui/mulh.S
+++ b/isa/rv32um/mulh.S
diff --git a/isa/rv32ui/mulhsu.S b/isa/rv32um/mulhsu.S
index 28b3690..28b3690 100644
--- a/isa/rv32ui/mulhsu.S
+++ b/isa/rv32um/mulhsu.S
diff --git a/isa/rv32ui/mulhu.S b/isa/rv32um/mulhu.S
index 601dcff..601dcff 100644
--- a/isa/rv32ui/mulhu.S
+++ b/isa/rv32um/mulhu.S
diff --git a/isa/rv32ui/rem.S b/isa/rv32um/rem.S
index c318e2c..c318e2c 100644
--- a/isa/rv32ui/rem.S
+++ b/isa/rv32um/rem.S
diff --git a/isa/rv32ui/remu.S b/isa/rv32um/remu.S
index 38d641d..38d641d 100644
--- a/isa/rv32ui/remu.S
+++ b/isa/rv32um/remu.S
diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S
index 5e4dfbb..77c9509 100644
--- a/isa/rv64mi/breakpoint.S
+++ b/isa/rv64mi/breakpoint.S
@@ -16,87 +16,117 @@ RVTEST_CODE_BEGIN
   # Set up breakpoint to trap on M-mode fetches.
   li TESTNUM, 2
 
-  # Skip tdrselect is hard-wired.
-  li t0, 1<<(_RISCV_SZLONG-1)
-  csrw tdrselect, t0
-  csrr t1, tdrselect
-  bne t0, t1, pass
+  # Skip tdrselect if hard-wired.
+  li a0, 1<<(_RISCV_SZLONG-1)
+  csrw tdrselect, a0
+  csrr a1, tdrselect
+  bne a0, a1, pass
 
   # Make sure there's a breakpoint there.
-  csrr t0, tdrdata1
-  srli t0, t0, _RISCV_SZLONG-4
-  li t1, 1
-  bne t0, t1, pass
-
-  la t2, 1f
-  csrw tdrdata2, t2
-  li t0, BPCONTROL_M | BPCONTROL_X
-  csrw tdrdata1, t0
+  csrr a0, tdrdata1
+  srli a0, a0, _RISCV_SZLONG-4
+  li a1, 1
+  bne a0, a1, pass
+
+  la a2, 1f
+  csrw tdrdata2, a2
+  li a0, BPCONTROL_M | BPCONTROL_X
+  csrw tdrdata1, a0
   # Skip if breakpoint type is unsupported.
-  csrr t1, tdrdata1
-  andi t1, t1, 0x7ff
-  bne t0, t1, 2f
+  csrr a1, tdrdata1
+  andi a1, a1, 0x7ff
+  bne a0, a1, 2f
 1:
   # Trap handler should skip this instruction.
   j fail
 
   # Make sure reads don't trap.
   li TESTNUM, 3
-  lw t0, (t2)
+  lw a0, (a2)
 
 2:
   # Set up breakpoint to trap on M-mode reads.
   li TESTNUM, 4
-  li t0, BPCONTROL_M | BPCONTROL_R
-  csrw tdrdata1, t0
+  li a0, BPCONTROL_M | BPCONTROL_R
+  csrw tdrdata1, a0
   # Skip if breakpoint type is unsupported.
-  csrr t1, tdrdata1
-  andi t1, t1, 0x7ff
-  bne t0, t1, 2f
-  la t2, write_data
-  csrw tdrdata2, t2
+  csrr a1, tdrdata1
+  andi a1, a1, 0x7ff
+  bne a0, a1, 2f
+  la a2, data1
+  csrw tdrdata2, a2
 
   # Trap handler should skip this instruction.
-  lw t2, (t2)
-  beqz t2, fail
+  lw a2, (a2)
+  beqz a2, fail
 
   # Make sure writes don't trap.
   li TESTNUM, 5
-  sw x0, (t2)
+  sw x0, (a2)
 
 2:
   # Set up breakpoint to trap on M-mode stores.
   li TESTNUM, 6
-  li t0, BPCONTROL_M | BPCONTROL_W
-  csrw tdrdata1, t0
+  li a0, BPCONTROL_M | BPCONTROL_W
+  csrw tdrdata1, a0
   # Skip if breakpoint type is unsupported.
-  csrr t1, tdrdata1
-  andi t1, t1, 0x7ff
-  bne t0, t1, 2f
+  csrr a1, tdrdata1
+  andi a1, a1, 0x7ff
+  bne a0, a1, 2f
 
   # Trap handler should skip this instruction.
-  sw t2, (t2)
+  sw a2, (a2)
 
   # Make sure store didn't succeed.
   li TESTNUM, 7
-  lw t2, (t2)
-  bnez t2, fail
+  lw a2, (a2)
+  bnez a2, fail
+
+  # Try to set up a second breakpoint.
+  li a0, (1<<(_RISCV_SZLONG-1)) + 1
+  csrw tdrselect, a0
+  csrr a1, tdrselect
+  bne a0, a1, pass
+
+  # Make sure there's a breakpoint there.
+  csrr a0, tdrdata1
+  srli a0, a0, _RISCV_SZLONG-4
+  li a1, 1
+  bne a0, a1, pass
+
+  li a0, BPCONTROL_M | BPCONTROL_R
+  csrw tdrdata1, a0
+  la a3, data2
+  csrw tdrdata2, a3
+
+  # Make sure the second breakpoint triggers.
+  li TESTNUM, 8
+  lw a3, (a3)
+  beqz a3, fail
+
+  # Make sure the first breakpoint still triggers.
+  li TESTNUM, 10
+  la a2, data1
+  sw a2, (a2)
+  li TESTNUM, 11
+  lw a2, (a2)
+  bnez a2, fail
 
 2:
   TEST_PASSFAIL
 
 mtvec_handler:
   # Only even-numbered tests should trap.
-  andi a0, TESTNUM, 1
-  bnez a0, fail
+  andi t0, TESTNUM, 1
+  bnez t0, fail
 
-  li a0, CAUSE_BREAKPOINT
-  csrr a1, mcause
-  bne a0, a1, fail
+  li t0, CAUSE_BREAKPOINT
+  csrr t1, mcause
+  bne t0, t1, fail
 
-  csrr a0, mepc
-  addi a0, a0, 4
-  csrw mepc, a0
+  csrr t0, mepc
+  addi t0, t0, 4
+  csrw mepc, t0
   mret
 
 RVTEST_CODE_END
@@ -106,6 +136,7 @@ RVTEST_DATA_BEGIN
 
   TEST_DATA
 
-write_data: .word 0
+data1: .word 0
+data2: .word 0
 
 RVTEST_DATA_END
diff --git a/isa/rv64mi/dirty.S b/isa/rv64mi/dirty.S
index 9de358b..66ed5a0 100644
--- a/isa/rv64mi/dirty.S
+++ b/isa/rv64mi/dirty.S
@@ -44,7 +44,7 @@ RVTEST_CODE_BEGIN
 
   # Make sure R and D bits are set
   lw t0, page_table_2
-  li t1, PTE_R | PTE_D
+  li t1, PTE_A | PTE_D
   and t0, t0, t1
   bne t0, t1, die
   
@@ -58,7 +58,7 @@ stvec_handler:
   bne TESTNUM, t1, 1f
   # Make sure R bit is set
   lw t0, page_table_1
-  li t1, PTE_R
+  li t1, PTE_A
   and t0, t0, t1
   bne t0, t1, die
 
@@ -84,9 +84,9 @@ RVTEST_DATA_BEGIN
   TEST_DATA
 
 .align 12
-page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_URX_SRX
+page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X
 dummy: .dword 0
 .align 12
-page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_URWX_SRWX
+page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_W
 
 RVTEST_DATA_END
diff --git a/isa/rv64si/wfi.S b/isa/rv64si/wfi.S
index 8e56909..0302034 100644
--- a/isa/rv64si/wfi.S
+++ b/isa/rv64si/wfi.S
@@ -13,9 +13,10 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  # Make sure wfi doesn't stall if an interrupt is pending, even if masked
+  # Make sure wfi doesn't halt the hart, even if interrupts are disabled
   csrc sstatus, SSTATUS_SIE
-  csrs sip, MIP_SSIP
+  csrs sie, SIP_SSIP
+  csrs sip, SIP_SSIP
   wfi
 
   RVTEST_PASS
diff --git a/isa/rv64ua/Makefrag b/isa/rv64ua/Makefrag
new file mode 100644
index 0000000..3af8856
--- /dev/null
+++ b/isa/rv64ua/Makefrag
@@ -0,0 +1,13 @@
+#=======================================================================
+# Makefrag for rv64ua tests
+#-----------------------------------------------------------------------
+
+rv64ua_sc_tests = \
+	amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \
+	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
+	lrsc \
+
+rv64ua_p_tests = $(addprefix rv64ua-p-, $(rv64ua_sc_tests))
+rv64ua_v_tests = $(addprefix rv64ua-v-, $(rv64ua_sc_tests))
+
+spike_tests += $(rv64ua_p_tests) $(rv64ua_v_tests)
diff --git a/isa/rv64ui/amoadd_d.S b/isa/rv64ua/amoadd_d.S
index c356bed..c356bed 100644
--- a/isa/rv64ui/amoadd_d.S
+++ b/isa/rv64ua/amoadd_d.S
diff --git a/isa/rv64ui/amoadd_w.S b/isa/rv64ua/amoadd_w.S
index b3d1953..b3d1953 100644
--- a/isa/rv64ui/amoadd_w.S
+++ b/isa/rv64ua/amoadd_w.S
diff --git a/isa/rv64ui/amoand_d.S b/isa/rv64ua/amoand_d.S
index 13019ae..13019ae 100644
--- a/isa/rv64ui/amoand_d.S
+++ b/isa/rv64ua/amoand_d.S
diff --git a/isa/rv64ui/amoand_w.S b/isa/rv64ua/amoand_w.S
index a843888..a843888 100644
--- a/isa/rv64ui/amoand_w.S
+++ b/isa/rv64ua/amoand_w.S
diff --git a/isa/rv64ui/amomax_d.S b/isa/rv64ua/amomax_d.S
index ea7e2d3..ea7e2d3 100644
--- a/isa/rv64ui/amomax_d.S
+++ b/isa/rv64ua/amomax_d.S
diff --git a/isa/rv64ui/amomax_w.S b/isa/rv64ua/amomax_w.S
index b3adbf0..b3adbf0 100644
--- a/isa/rv64ui/amomax_w.S
+++ b/isa/rv64ua/amomax_w.S
diff --git a/isa/rv64ui/amomaxu_d.S b/isa/rv64ua/amomaxu_d.S
index b340873..b340873 100644
--- a/isa/rv64ui/amomaxu_d.S
+++ b/isa/rv64ua/amomaxu_d.S
diff --git a/isa/rv64ui/amomaxu_w.S b/isa/rv64ua/amomaxu_w.S
index 41346d1..41346d1 100644
--- a/isa/rv64ui/amomaxu_w.S
+++ b/isa/rv64ua/amomaxu_w.S
diff --git a/isa/rv64ui/amomin_d.S b/isa/rv64ua/amomin_d.S
index e6febbb..e6febbb 100644
--- a/isa/rv64ui/amomin_d.S
+++ b/isa/rv64ua/amomin_d.S
diff --git a/isa/rv64ui/amomin_w.S b/isa/rv64ua/amomin_w.S
index 96b547b..96b547b 100644
--- a/isa/rv64ui/amomin_w.S
+++ b/isa/rv64ua/amomin_w.S
diff --git a/isa/rv64ui/amominu_d.S b/isa/rv64ua/amominu_d.S
index a1013f3..a1013f3 100644
--- a/isa/rv64ui/amominu_d.S
+++ b/isa/rv64ua/amominu_d.S
diff --git a/isa/rv64ui/amominu_w.S b/isa/rv64ua/amominu_w.S
index 0a9e265..0a9e265 100644
--- a/isa/rv64ui/amominu_w.S
+++ b/isa/rv64ua/amominu_w.S
diff --git a/isa/rv64ui/amoor_d.S b/isa/rv64ua/amoor_d.S
index 507e877..507e877 100644
--- a/isa/rv64ui/amoor_d.S
+++ b/isa/rv64ua/amoor_d.S
diff --git a/isa/rv64ui/amoor_w.S b/isa/rv64ua/amoor_w.S
index 47978ba..47978ba 100644
--- a/isa/rv64ui/amoor_w.S
+++ b/isa/rv64ua/amoor_w.S
diff --git a/isa/rv64ui/amoswap_d.S b/isa/rv64ua/amoswap_d.S
index 628f537..628f537 100644
--- a/isa/rv64ui/amoswap_d.S
+++ b/isa/rv64ua/amoswap_d.S
diff --git a/isa/rv64ui/amoswap_w.S b/isa/rv64ua/amoswap_w.S
index c09b866..c09b866 100644
--- a/isa/rv64ui/amoswap_w.S
+++ b/isa/rv64ua/amoswap_w.S
diff --git a/isa/rv64ui/amoxor_d.S b/isa/rv64ua/amoxor_d.S
index f446121..f446121 100644
--- a/isa/rv64ui/amoxor_d.S
+++ b/isa/rv64ua/amoxor_d.S
diff --git a/isa/rv64ui/amoxor_w.S b/isa/rv64ua/amoxor_w.S
index 2b92323..2b92323 100644
--- a/isa/rv64ui/amoxor_w.S
+++ b/isa/rv64ua/amoxor_w.S
diff --git a/isa/rv64ui/lrsc.S b/isa/rv64ua/lrsc.S
index 9422739..9422739 100644
--- a/isa/rv64ui/lrsc.S
+++ b/isa/rv64ua/lrsc.S
diff --git a/isa/rv64ud/Makefrag b/isa/rv64ud/Makefrag
new file mode 100644
index 0000000..6e8be9c
--- /dev/null
+++ b/isa/rv64ud/Makefrag
@@ -0,0 +1,12 @@
+#=======================================================================
+# Makefrag for rv64ud tests
+#-----------------------------------------------------------------------
+
+rv64ud_sc_tests = \
+	fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin fsgnj \
+	ldst move structural recoding \
+
+rv64ud_p_tests = $(addprefix rv64ud-p-, $(rv64ud_sc_tests))
+rv64ud_v_tests = $(addprefix rv64ud-v-, $(rv64ud_sc_tests))
+
+spike_tests += $(rv64ud_p_tests) $(rv64ud_v_tests)
diff --git a/isa/rv64ud/fadd.S b/isa/rv64ud/fadd.S
new file mode 100644
index 0000000..4a314da
--- /dev/null
+++ b/isa/rv64ud/fadd.S
@@ -0,0 +1,44 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f{add|sub|mul}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_D( 2,  fadd.d, 0,                3.5,        2.5,        1.0 );
+  TEST_FP_OP2_D( 3,  fadd.d, 1,              -1234,    -1235.1,        1.1 );
+  TEST_FP_OP2_D( 4,  fadd.d, 1,         3.14159266, 3.14159265, 0.00000001 );
+
+  TEST_FP_OP2_D( 5,  fsub.d, 0,                1.5,        2.5,        1.0 );
+  TEST_FP_OP2_D( 6,  fsub.d, 1,              -1234,    -1235.1,       -1.1 );
+  TEST_FP_OP2_D( 7,  fsub.d, 1, 3.1415926400000001, 3.14159265, 0.00000001 );
+
+  TEST_FP_OP2_D( 8,  fmul.d, 0,                2.5,        2.5,        1.0 );
+  TEST_FP_OP2_D( 9,  fmul.d, 1,            1358.61,    -1235.1,       -1.1 );
+  TEST_FP_OP2_D(10,  fmul.d, 1,      3.14159265e-8, 3.14159265, 0.00000001 );
+
+  # Is the canonical NaN generated for Inf - Inf?
+  TEST_FP_OP2_D(11,  fsub.d, 0x10, 0d:7ff8000000000000, Inf, Inf);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ud/fclass.S b/isa/rv64ud/fclass.S
new file mode 100644
index 0000000..3daace0
--- /dev/null
+++ b/isa/rv64ud/fclass.S
@@ -0,0 +1,44 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fclass.S
+#-----------------------------------------------------------------------------
+#
+# Test fclass.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  #define TEST_FCLASS_D(testnum, correct, input) \
+    TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \
+                                    fclass.d a0, fa0)
+
+  TEST_FCLASS_D( 2, 1 << 0, 0xfff0000000000000 )
+  TEST_FCLASS_D( 3, 1 << 1, 0xbff0000000000000 )
+  TEST_FCLASS_D( 4, 1 << 2, 0x800fffffffffffff )
+  TEST_FCLASS_D( 5, 1 << 3, 0x8000000000000000 )
+  TEST_FCLASS_D( 6, 1 << 4, 0x0000000000000000 )
+  TEST_FCLASS_D( 7, 1 << 5, 0x000fffffffffffff )
+  TEST_FCLASS_D( 8, 1 << 6, 0x3ff0000000000000 )
+  TEST_FCLASS_D( 9, 1 << 7, 0x7ff0000000000000 )
+  TEST_FCLASS_D(10, 1 << 8, 0x7ff0000000000001 )
+  TEST_FCLASS_D(11, 1 << 9, 0x7ff8000000000000 )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ud/fcmp.S b/isa/rv64ud/fcmp.S
new file mode 100644
index 0000000..173dc88
--- /dev/null
+++ b/isa/rv64ud/fcmp.S
@@ -0,0 +1,37 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcmp.S
+#-----------------------------------------------------------------------------
+#
+# Test f{eq|lt|le}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_CMP_OP_D( 2, feq.d, 1, -1.36, -1.36)
+  TEST_FP_CMP_OP_D( 3, fle.d, 1, -1.36, -1.36)
+  TEST_FP_CMP_OP_D( 4, flt.d, 0, -1.36, -1.36)
+
+  TEST_FP_CMP_OP_D( 5, feq.d, 0, -1.37, -1.36)
+  TEST_FP_CMP_OP_D( 6, fle.d, 1, -1.37, -1.36)
+  TEST_FP_CMP_OP_D( 7, flt.d, 1, -1.37, -1.36)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ud/fcvt.S b/isa/rv64ud/fcvt.S
new file mode 100644
index 0000000..4f25d07
--- /dev/null
+++ b/isa/rv64ud/fcvt.S
@@ -0,0 +1,56 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcvt.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt.d.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_INT_FP_OP_D(2,  fcvt.d.w,                   2.0,  2);
+  TEST_INT_FP_OP_D(3,  fcvt.d.w,                  -2.0, -2);
+
+  TEST_INT_FP_OP_D(4, fcvt.d.wu,                   2.0,  2);
+  TEST_INT_FP_OP_D(5, fcvt.d.wu,            4294967294, -2);
+
+  TEST_INT_FP_OP_D(6,  fcvt.d.l,                   2.0,  2);
+  TEST_INT_FP_OP_D(7,  fcvt.d.l,                  -2.0, -2);
+
+  TEST_INT_FP_OP_D(8, fcvt.d.lu,                   2.0,  2);
+  TEST_INT_FP_OP_D(9, fcvt.d.lu, 1.8446744073709552e19, -2);
+
+  TEST_FCVT_S_D(10, -1.5, -1.5)
+  TEST_FCVT_D_S(11, -1.5, -1.5)
+
+  TEST_CASE(12, a0, 0x7ff8000000000000,
+    la a1, test_data_22;
+    ld a2, 0(a1);
+    fmv.d.x f2, a2;
+    fcvt.s.d f2, f2;
+    fcvt.d.s f2, f2;
+    fmv.x.d a0, f2;
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+test_data_22:
+  .dword 0x7ffcffffffff8004
+
+RVTEST_DATA_END
diff --git a/isa/rv64ud/fcvt_w.S b/isa/rv64ud/fcvt_w.S
new file mode 100644
index 0000000..50e794c
--- /dev/null
+++ b/isa/rv64ud/fcvt_w.S
@@ -0,0 +1,102 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcvt_w.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt{wu|w|lu|l}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_INT_OP_D( 2,  fcvt.w.d, 0x01,         -1, -1.1, rtz);
+  TEST_FP_INT_OP_D( 3,  fcvt.w.d, 0x00,         -1, -1.0, rtz);
+  TEST_FP_INT_OP_D( 4,  fcvt.w.d, 0x01,          0, -0.9, rtz);
+  TEST_FP_INT_OP_D( 5,  fcvt.w.d, 0x01,          0,  0.9, rtz);
+  TEST_FP_INT_OP_D( 6,  fcvt.w.d, 0x00,          1,  1.0, rtz);
+  TEST_FP_INT_OP_D( 7,  fcvt.w.d, 0x01,          1,  1.1, rtz);
+  TEST_FP_INT_OP_D( 8,  fcvt.w.d, 0x10,     -1<<31, -3e9, rtz);
+  TEST_FP_INT_OP_D( 9,  fcvt.w.d, 0x10,  (1<<31)-1,  3e9, rtz);
+
+  TEST_FP_INT_OP_D(12, fcvt.wu.d, 0x10,          0, -3.0, rtz);
+  TEST_FP_INT_OP_D(13, fcvt.wu.d, 0x10,          0, -1.0, rtz);
+  TEST_FP_INT_OP_D(14, fcvt.wu.d, 0x01,          0, -0.9, rtz);
+  TEST_FP_INT_OP_D(15, fcvt.wu.d, 0x01,          0,  0.9, rtz);
+  TEST_FP_INT_OP_D(16, fcvt.wu.d, 0x00,          1,  1.0, rtz);
+  TEST_FP_INT_OP_D(17, fcvt.wu.d, 0x01,          1,  1.1, rtz);
+  TEST_FP_INT_OP_D(18, fcvt.wu.d, 0x10,          0, -3e9, rtz);
+  TEST_FP_INT_OP_D(19, fcvt.wu.d, 0x00, 0xffffffffb2d05e00, 3e9, rtz);
+
+  TEST_FP_INT_OP_D(22,  fcvt.l.d, 0x01,         -1, -1.1, rtz);
+  TEST_FP_INT_OP_D(23,  fcvt.l.d, 0x00,         -1, -1.0, rtz);
+  TEST_FP_INT_OP_D(24,  fcvt.l.d, 0x01,          0, -0.9, rtz);
+  TEST_FP_INT_OP_D(25,  fcvt.l.d, 0x01,          0,  0.9, rtz);
+  TEST_FP_INT_OP_D(26,  fcvt.l.d, 0x00,          1,  1.0, rtz);
+  TEST_FP_INT_OP_D(27,  fcvt.l.d, 0x01,          1,  1.1, rtz);
+  TEST_FP_INT_OP_D(28,  fcvt.l.d, 0x00,-3000000000, -3e9, rtz);
+  TEST_FP_INT_OP_D(29,  fcvt.l.d, 0x00, 3000000000,  3e9, rtz);
+  TEST_FP_INT_OP_D(20,  fcvt.l.d, 0x10,     -1<<63,-3e19, rtz);
+  TEST_FP_INT_OP_D(21,  fcvt.l.d, 0x10,  (1<<63)-1, 3e19, rtz);
+
+  TEST_FP_INT_OP_D(32, fcvt.lu.d, 0x10,          0, -3.0, rtz);
+  TEST_FP_INT_OP_D(33, fcvt.lu.d, 0x10,          0, -1.0, rtz);
+  TEST_FP_INT_OP_D(34, fcvt.lu.d, 0x01,          0, -0.9, rtz);
+  TEST_FP_INT_OP_D(35, fcvt.lu.d, 0x01,          0,  0.9, rtz);
+  TEST_FP_INT_OP_D(36, fcvt.lu.d, 0x00,          1,  1.0, rtz);
+  TEST_FP_INT_OP_D(37, fcvt.lu.d, 0x01,          1,  1.1, rtz);
+  TEST_FP_INT_OP_D(38, fcvt.lu.d, 0x10,          0, -3e9, rtz);
+  TEST_FP_INT_OP_D(39, fcvt.lu.d, 0x00, 3000000000,  3e9, rtz);
+
+  # test negative NaN, negative infinity conversion
+  TEST_CASE(42, x1, 0x000000007fffffff, la x1, tdat_d; fld f1,  0(x1); fcvt.w.d x1, f1)
+  TEST_CASE(43, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1,  0(x1); fcvt.l.d x1, f1)
+  TEST_CASE(44, x1, 0xffffffff80000000, la x1, tdat_d; fld f1, 16(x1); fcvt.w.d x1, f1)
+  TEST_CASE(45, x1, 0x8000000000000000, la x1, tdat_d; fld f1, 16(x1); fcvt.l.d x1, f1)
+
+  # test positive NaN, positive infinity conversion
+  TEST_CASE(52, x1, 0x000000007fffffff, la x1, tdat_d; fld f1,  8(x1); fcvt.w.d x1, f1)
+  TEST_CASE(53, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1,  8(x1); fcvt.l.d x1, f1)
+  TEST_CASE(54, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.w.d x1, f1)
+  TEST_CASE(55, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.l.d x1, f1)
+
+  # test NaN, infinity conversions to unsigned integer
+  TEST_CASE(62, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1,  0(x1); fcvt.wu.d x1, f1)
+  TEST_CASE(63, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1,  8(x1); fcvt.wu.d x1, f1)
+  TEST_CASE(64, x1,                  0, la x1, tdat_d; fld f1, 16(x1); fcvt.wu.d x1, f1)
+  TEST_CASE(65, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.wu.d x1, f1)
+  TEST_CASE(66, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1,  0(x1); fcvt.lu.d x1, f1)
+  TEST_CASE(67, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1,  8(x1); fcvt.lu.d x1, f1)
+  TEST_CASE(68, x1,                  0, la x1, tdat_d; fld f1, 16(x1); fcvt.lu.d x1, f1)
+  TEST_CASE(69, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.lu.d x1, f1)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+# -NaN, NaN, -inf, +inf
+tdat:
+.word 0xffffffff
+.word 0x7fffffff
+.word 0xff800000
+.word 0x7f800000
+
+tdat_d:
+.dword 0xffffffffffffffff
+.dword 0x7fffffffffffffff
+.dword 0xfff0000000000000
+.dword 0x7ff0000000000000
+
+RVTEST_DATA_END
diff --git a/isa/rv64ud/fdiv.S b/isa/rv64ud/fdiv.S
new file mode 100644
index 0000000..8a9fd4d
--- /dev/null
+++ b/isa/rv64ud/fdiv.S
@@ -0,0 +1,42 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fdiv.S
+#-----------------------------------------------------------------------------
+#
+# Test f{div|sqrt}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_D( 2,  fdiv.d, 1, 1.1557273520668288, 3.14159265, 2.71828182 );
+  TEST_FP_OP2_D( 3,  fdiv.d, 1,-0.9991093838555584,      -1234,     1235.1 );
+  TEST_FP_OP2_D( 4,  fdiv.d, 0,         3.14159265, 3.14159265,        1.0 );
+
+  TEST_FP_OP1_D( 5,  fsqrt.d, 1, 1.7724538498928541, 3.14159265 );
+  TEST_FP_OP1_D( 6,  fsqrt.d, 0,                100,      10000 );
+
+  TEST_FP_OP1_D_DWORD_RESULT(16,  fsqrt.d, 0x10,      0x7FF8000000000000,      -1.0 );
+
+  TEST_FP_OP1_D( 7,  fsqrt.d, 1, 13.076696830622021, 171.0);
+
+  TEST_FP_OP1_D( 8,  fsqrt.d, 1,0.00040099251863345283320230749702, 1.60795e-7);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ud/fmadd.S b/isa/rv64ud/fmadd.S
new file mode 100644
index 0000000..7a69aad
--- /dev/null
+++ b/isa/rv64ud/fmadd.S
@@ -0,0 +1,45 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP3_D( 2,  fmadd.d, 0,                 3.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_D( 3,  fmadd.d, 1,  1236.1999999999999, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_D( 4,  fmadd.d, 0,               -12.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_D( 5, fnmadd.d, 0,                -3.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_D( 6, fnmadd.d, 1, -1236.1999999999999, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_D( 7, fnmadd.d, 0,                12.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_D( 8,  fmsub.d, 0,                 1.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_D( 9,  fmsub.d, 1,                1234, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_D(10,  fmsub.d, 0,                -8.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_D(11, fnmsub.d, 0,                -1.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_D(12, fnmsub.d, 1,               -1234, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_D(13, fnmsub.d, 0,                 8.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ud/fmin.S b/isa/rv64ud/fmin.S
new file mode 100644
index 0000000..82641bc
--- /dev/null
+++ b/isa/rv64ud/fmin.S
@@ -0,0 +1,43 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmin.S
+#-----------------------------------------------------------------------------
+#
+# Test f{min|max}.d instructinos.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_D( 2,  fmin.d, 0,        1.0,        2.5,        1.0 );
+  TEST_FP_OP2_D( 3,  fmin.d, 0,    -1235.1,    -1235.1,        1.1 );
+  TEST_FP_OP2_D( 4,  fmin.d, 0,    -1235.1,        1.1,    -1235.1 );
+  TEST_FP_OP2_D( 5,  fmin.d, 0,    -1235.1,        NaN,    -1235.1 );
+  TEST_FP_OP2_D( 6,  fmin.d, 0, 0.00000001, 3.14159265, 0.00000001 );
+  TEST_FP_OP2_D( 7,  fmin.d, 0,       -2.0,       -1.0,       -2.0 );
+
+  TEST_FP_OP2_D(12,  fmax.d, 0,        2.5,        2.5,        1.0 );
+  TEST_FP_OP2_D(13,  fmax.d, 0,        1.1,    -1235.1,        1.1 );
+  TEST_FP_OP2_D(14,  fmax.d, 0,        1.1,        1.1,    -1235.1 );
+  TEST_FP_OP2_D(15,  fmax.d, 0,    -1235.1,        NaN,    -1235.1 );
+  TEST_FP_OP2_D(16,  fmax.d, 0, 3.14159265, 3.14159265, 0.00000001 );
+  TEST_FP_OP2_D(17,  fmax.d, 0,       -1.0,       -1.0,       -2.0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ud/fsgnj.S b/isa/rv64ud/fsgnj.S
new file mode 100644
index 0000000..e914777
--- /dev/null
+++ b/isa/rv64ud/fsgnj.S
@@ -0,0 +1,44 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fsgnj.S
+#-----------------------------------------------------------------------------
+#
+# Test fsgn{j|jn|x}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_D( 2,  fsgnj.d, 0, -6.3,  6.3, -1.0 );
+  TEST_FP_OP2_D( 3,  fsgnj.d, 0,  7.3,  7.3,  2.0 );
+  TEST_FP_OP2_D( 4,  fsgnj.d, 0, -8.3, -8.3, -3.0 );
+  TEST_FP_OP2_D( 5,  fsgnj.d, 0,  9.3, -9.3,  4.0 );
+
+  TEST_FP_OP2_D(12, fsgnjn.d, 0,  6.3,  6.3, -1.0 );
+  TEST_FP_OP2_D(13, fsgnjn.d, 0, -7.3,  7.3,  2.0 );
+  TEST_FP_OP2_D(14, fsgnjn.d, 0,  8.3, -8.3, -3.0 );
+  TEST_FP_OP2_D(15, fsgnjn.d, 0, -9.3, -9.3,  4.0 );
+
+  TEST_FP_OP2_D(22, fsgnjx.d, 0, -6.3,  6.3, -1.0 );
+  TEST_FP_OP2_D(23, fsgnjx.d, 0,  7.3,  7.3,  2.0 );
+  TEST_FP_OP2_D(24, fsgnjx.d, 0,  8.3, -8.3, -3.0 );
+  TEST_FP_OP2_D(25, fsgnjx.d, 0, -9.3, -9.3,  4.0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ud/ldst.S b/isa/rv64ud/ldst.S
new file mode 100644
index 0000000..59084e3
--- /dev/null
+++ b/isa/rv64ud/ldst.S
@@ -0,0 +1,38 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a0, 0x40000000bf800000, la a1, tdat; fld f2, 0(a1); fsd f2, 16(a1); ld a0, 16(a1))
+  TEST_CASE(3, a0, 0xc080000040400000, la a1, tdat; fld f2, 8(a1); fsd f2, 16(a1); ld a0, 16(a1))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+.word 0xbf800000
+.word 0x40000000
+.word 0x40400000
+.word 0xc0800000
+.word 0xdeadbeef
+.word 0xcafebabe
+.word 0xabad1dea
+.word 0x1337d00d
+
+RVTEST_DATA_END
diff --git a/isa/rv64ud/move.S b/isa/rv64ud/move.S
new file mode 100644
index 0000000..806d4de
--- /dev/null
+++ b/isa/rv64ud/move.S
@@ -0,0 +1,36 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# move.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that mxtf.[s,d], mftx.[s,d], fssr, frsr,
+# and fsgnj[x|n].d work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+li a0, 1
+fssr a0
+
+  TEST_CASE(2, a1, 1, li a0, 0x1234; fssr a1, a0)
+  TEST_CASE(3, a0, 0x34, frsr a0)
+  TEST_CASE(4, a0, 0x34, frsr a0)
+
+  TEST_CASE(5, a0, 0x3FF02468A0000000, li a1, 0x3FF02468A0000000; fmv.d.x f1, a1; fmv.x.d a0, f1)
+  TEST_CASE(6, a0, 0xBFF02468A0001000, li a1, 0x3FF02468A0001000; li a2, -1; fmv.d.x f1, a1; fmv.d.x f2, a2; fsgnj.d f0, f1, f2; fmv.x.d a0, f0)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ud/recoding.S b/isa/rv64ud/recoding.S
new file mode 100644
index 0000000..69ad665
--- /dev/null
+++ b/isa/rv64ud/recoding.S
@@ -0,0 +1,67 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# recoding.S
+#-----------------------------------------------------------------------------
+#
+# Test corner cases of John Hauser's microarchitectural recoding scheme.
+# There are twice as many recoded values as IEEE-754 values; some of these
+# extras are redundant (e.g. Inf) and others are illegal (subnormals with
+# too many bits set).
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  # Make sure infinities with different mantissas compare as equal.
+  fld f0, minf, a0
+  fld f1, three, a0
+  fmul.d f1, f1, f0
+  TEST_CASE( 2, a0, 1, feq.d a0, f0, f1)
+  TEST_CASE( 3, a0, 1, fle.d a0, f0, f1)
+  TEST_CASE( 4, a0, 0, flt.d a0, f0, f1)
+
+  # Likewise, but for zeroes.
+  fcvt.d.w f0, x0
+  li a0, 1
+  fcvt.d.w f1, a0
+  fmul.d f1, f1, f0
+  TEST_CASE(5, a0, 1, feq.d a0, f0, f1)
+  TEST_CASE(6, a0, 1, fle.d a0, f0, f1)
+  TEST_CASE(7, a0, 0, flt.d a0, f0, f1)
+
+  # When converting small doubles to single-precision subnormals,
+  # ensure that the extra precision is discarded.
+  flw f0, big, a0
+  fld f1, tiny, a0
+  fcvt.s.d f1, f1
+  fmul.s f0, f0, f1
+  fmv.x.s a0, f0
+  lw a1, small
+  TEST_CASE(10, a0, 0, sub a0, a0, a1)
+
+  # Make sure FSD+FLD correctly saves and restores a single-precision value.
+  flw f0, three, a0
+  fadd.s f1, f0, f0
+  fadd.s f0, f0, f0
+  fsd f0, tiny, a0
+  fld f0, tiny, a0
+  TEST_CASE(20, a0, 1, feq.s a0, f0, f1)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+minf: .double -Inf
+three: .double 3.0
+big: .float 1221
+small: .float 2.9133121e-37
+tiny: .double 2.3860049081905093e-40
+
+RVTEST_DATA_END
diff --git a/isa/rv64uf/structural.S b/isa/rv64ud/structural.S
index 76c6691..76c6691 100644
--- a/isa/rv64uf/structural.S
+++ b/isa/rv64ud/structural.S
diff --git a/isa/rv64uf/Makefrag b/isa/rv64uf/Makefrag
index 978084a..d3c3f23 100644
--- a/isa/rv64uf/Makefrag
+++ b/isa/rv64uf/Makefrag
@@ -4,7 +4,7 @@
 
 rv64uf_sc_tests = \
 	fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin fsgnj \
-	ldst move structural recoding \
+	ldst move recoding \
 
 rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests))
 rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests))
diff --git a/isa/rv64uf/fadd.S b/isa/rv64uf/fadd.S
index a5f3e42..800dc8c 100644
--- a/isa/rv64uf/fadd.S
+++ b/isa/rv64uf/fadd.S
@@ -4,7 +4,7 @@
 # fadd.S
 #-----------------------------------------------------------------------------
 #
-# Test f{add|sub|mul}.{s|d} instructions.
+# Test f{add|sub|mul}.s instructions.
 #
 
 #include "riscv_test.h"
@@ -21,29 +21,16 @@ RVTEST_CODE_BEGIN
   TEST_FP_OP2_S( 3,  fadd.s, 1,              -1234,    -1235.1,        1.1 );
   TEST_FP_OP2_S( 4,  fadd.s, 1,         3.14159265, 3.14159265, 0.00000001 );
 
-  TEST_FP_OP2_D( 5,  fadd.d, 0,                3.5,        2.5,        1.0 );
-  TEST_FP_OP2_D( 6,  fadd.d, 1,              -1234,    -1235.1,        1.1 );
-  TEST_FP_OP2_D( 7,  fadd.d, 1,         3.14159266, 3.14159265, 0.00000001 );
+  TEST_FP_OP2_S( 5,  fsub.s, 0,                1.5,        2.5,        1.0 );
+  TEST_FP_OP2_S( 6,  fsub.s, 1,              -1234,    -1235.1,       -1.1 );
+  TEST_FP_OP2_S( 7,  fsub.s, 1,         3.14159265, 3.14159265, 0.00000001 );
 
-  TEST_FP_OP2_S(12,  fsub.s, 0,                1.5,        2.5,        1.0 );
-  TEST_FP_OP2_S(13,  fsub.s, 1,              -1234,    -1235.1,       -1.1 );
-  TEST_FP_OP2_S(14,  fsub.s, 1,         3.14159265, 3.14159265, 0.00000001 );
-
-  TEST_FP_OP2_D(15,  fsub.d, 0,                1.5,        2.5,        1.0 );
-  TEST_FP_OP2_D(16,  fsub.d, 1,              -1234,    -1235.1,       -1.1 );
-  TEST_FP_OP2_D(17,  fsub.d, 1, 3.1415926400000001, 3.14159265, 0.00000001 );
-
-  TEST_FP_OP2_S(22,  fmul.s, 0,                2.5,        2.5,        1.0 );
-  TEST_FP_OP2_S(23,  fmul.s, 1,            1358.61,    -1235.1,       -1.1 );
-  TEST_FP_OP2_S(24,  fmul.s, 1,      3.14159265e-8, 3.14159265, 0.00000001 );
-
-  TEST_FP_OP2_D(25,  fmul.d, 0,                2.5,        2.5,        1.0 );
-  TEST_FP_OP2_D(26,  fmul.d, 1,            1358.61,    -1235.1,       -1.1 );
-  TEST_FP_OP2_D(27,  fmul.d, 1,      3.14159265e-8, 3.14159265, 0.00000001 );
+  TEST_FP_OP2_S( 8,  fmul.s, 0,                2.5,        2.5,        1.0 );
+  TEST_FP_OP2_S( 9,  fmul.s, 1,            1358.61,    -1235.1,       -1.1 );
+  TEST_FP_OP2_S(10,  fmul.s, 1,      3.14159265e-8, 3.14159265, 0.00000001 );
 
   # Is the canonical NaN generated for Inf - Inf?
-  TEST_FP_OP2_S(28,  fsub.s, 0x10,         0f:7fc00000, Inf, Inf);
-  TEST_FP_OP2_D(29,  fsub.d, 0x10, 0d:7ff8000000000000, Inf, Inf);
+  TEST_FP_OP2_S(11,  fsub.s, 0x10,         0f:7fc00000, Inf, Inf);
 
   TEST_PASSFAIL
 
diff --git a/isa/rv64uf/fclass.S b/isa/rv64uf/fclass.S
index bcebbf8..5a6361e 100644
--- a/isa/rv64uf/fclass.S
+++ b/isa/rv64uf/fclass.S
@@ -4,7 +4,7 @@
 # fclass.S
 #-----------------------------------------------------------------------------
 #
-# Test fclass.{s|d} instructions.
+# Test fclass.s instructions.
 #
 
 #include "riscv_test.h"
@@ -32,21 +32,6 @@ RVTEST_CODE_BEGIN
   TEST_FCLASS_S(10, 1 << 8, 0x7f800001 )
   TEST_FCLASS_S(11, 1 << 9, 0x7fc00000 )
 
-  #define TEST_FCLASS_D(testnum, correct, input) \
-    TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \
-                                    fclass.d a0, fa0)
-
-  TEST_FCLASS_D(12, 1 << 0, 0xfff0000000000000 )
-  TEST_FCLASS_D(13, 1 << 1, 0xbff0000000000000 )
-  TEST_FCLASS_D(14, 1 << 2, 0x800fffffffffffff )
-  TEST_FCLASS_D(15, 1 << 3, 0x8000000000000000 )
-  TEST_FCLASS_D(16, 1 << 4, 0x0000000000000000 )
-  TEST_FCLASS_D(17, 1 << 5, 0x000fffffffffffff )
-  TEST_FCLASS_D(18, 1 << 6, 0x3ff0000000000000 )
-  TEST_FCLASS_D(19, 1 << 7, 0x7ff0000000000000 )
-  TEST_FCLASS_D(20, 1 << 8, 0x7ff0000000000001 )
-  TEST_FCLASS_D(21, 1 << 9, 0x7ff8000000000000 )
-
   TEST_PASSFAIL
 
 RVTEST_CODE_END
diff --git a/isa/rv64uf/fcmp.S b/isa/rv64uf/fcmp.S
index 252ad29..24b08c7 100644
--- a/isa/rv64uf/fcmp.S
+++ b/isa/rv64uf/fcmp.S
@@ -4,7 +4,7 @@
 # fcmp.S
 #-----------------------------------------------------------------------------
 #
-# Test f{eq|lt|le}.{s|d} instructions.
+# Test f{eq|lt|le}.s instructions.
 #
 
 #include "riscv_test.h"
diff --git a/isa/rv64uf/fcvt.S b/isa/rv64uf/fcvt.S
index cbaf6d3..7bcb49a 100644
--- a/isa/rv64uf/fcvt.S
+++ b/isa/rv64uf/fcvt.S
@@ -4,7 +4,7 @@
 # fcvt.S
 #-----------------------------------------------------------------------------
 #
-# Test fcvt.{s|d}.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions.
+# Test fcvt.s.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions.
 #
 
 #include "riscv_test.h"
@@ -29,30 +29,6 @@ RVTEST_CODE_BEGIN
   TEST_INT_FP_OP_S( 8, fcvt.s.lu,                   2.0,  2);
   TEST_INT_FP_OP_S( 9, fcvt.s.lu,          1.8446744e19, -2);
 
-  TEST_INT_FP_OP_D(12,  fcvt.d.w,                   2.0,  2);
-  TEST_INT_FP_OP_D(13,  fcvt.d.w,                  -2.0, -2);
-
-  TEST_INT_FP_OP_D(14, fcvt.d.wu,                   2.0,  2);
-  TEST_INT_FP_OP_D(15, fcvt.d.wu,            4294967294, -2);
-
-  TEST_INT_FP_OP_D(16,  fcvt.d.l,                   2.0,  2);
-  TEST_INT_FP_OP_D(17,  fcvt.d.l,                  -2.0, -2);
-
-  TEST_INT_FP_OP_D(18, fcvt.d.lu,                   2.0,  2);
-  TEST_INT_FP_OP_D(19, fcvt.d.lu, 1.8446744073709552e19, -2);
-
-  TEST_FCVT_S_D(20, -1.5, -1.5)
-  TEST_FCVT_D_S(21, -1.5, -1.5)
-
-  TEST_CASE(22, a0, 0x7ff8000000000000,
-    la a1, test_data_22;
-    ld a2, 0(a1);
-    fmv.d.x f2, a2;
-    fcvt.s.d f2, f2;
-    fcvt.d.s f2, f2;
-    fmv.x.d a0, f2;
-  )
-
   TEST_PASSFAIL
 
 RVTEST_CODE_END
@@ -62,7 +38,4 @@ RVTEST_DATA_BEGIN
 
   TEST_DATA
 
-test_data_22:
-  .dword 0x7ffcffffffff8004
-
 RVTEST_DATA_END
diff --git a/isa/rv64uf/fcvt_w.S b/isa/rv64uf/fcvt_w.S
index 7b78eec..92faffa 100644
--- a/isa/rv64uf/fcvt_w.S
+++ b/isa/rv64uf/fcvt_w.S
@@ -4,7 +4,7 @@
 # fcvt_w.S
 #-----------------------------------------------------------------------------
 #
-# Test fcvt{wu|w|lu|l}.{s|d} instructions.
+# Test fcvt{wu|w|lu|l}.s instructions.
 #
 
 #include "riscv_test.h"
@@ -50,85 +50,28 @@ RVTEST_CODE_BEGIN
   TEST_FP_INT_OP_S(37, fcvt.lu.s, 0x01,          1,  1.1, rtz);
   TEST_FP_INT_OP_S(38, fcvt.lu.s, 0x10,          0, -3e9, rtz);
 
-  TEST_FP_INT_OP_D(42,  fcvt.w.d, 0x01,         -1, -1.1, rtz);
-  TEST_FP_INT_OP_D(43,  fcvt.w.d, 0x00,         -1, -1.0, rtz);
-  TEST_FP_INT_OP_D(44,  fcvt.w.d, 0x01,          0, -0.9, rtz);
-  TEST_FP_INT_OP_D(45,  fcvt.w.d, 0x01,          0,  0.9, rtz);
-  TEST_FP_INT_OP_D(46,  fcvt.w.d, 0x00,          1,  1.0, rtz);
-  TEST_FP_INT_OP_D(47,  fcvt.w.d, 0x01,          1,  1.1, rtz);
-  TEST_FP_INT_OP_D(48,  fcvt.w.d, 0x10,     -1<<31, -3e9, rtz);
-  TEST_FP_INT_OP_D(49,  fcvt.w.d, 0x10,  (1<<31)-1,  3e9, rtz);
-
-  TEST_FP_INT_OP_D(52, fcvt.wu.d, 0x10,          0, -3.0, rtz);
-  TEST_FP_INT_OP_D(53, fcvt.wu.d, 0x10,          0, -1.0, rtz);
-  TEST_FP_INT_OP_D(54, fcvt.wu.d, 0x01,          0, -0.9, rtz);
-  TEST_FP_INT_OP_D(55, fcvt.wu.d, 0x01,          0,  0.9, rtz);
-  TEST_FP_INT_OP_D(56, fcvt.wu.d, 0x00,          1,  1.0, rtz);
-  TEST_FP_INT_OP_D(57, fcvt.wu.d, 0x01,          1,  1.1, rtz);
-  TEST_FP_INT_OP_D(58, fcvt.wu.d, 0x10,          0, -3e9, rtz);
-  TEST_FP_INT_OP_D(59, fcvt.wu.d, 0x00, 0xffffffffb2d05e00, 3e9, rtz);
-
-  TEST_FP_INT_OP_D(62,  fcvt.l.d, 0x01,         -1, -1.1, rtz);
-  TEST_FP_INT_OP_D(63,  fcvt.l.d, 0x00,         -1, -1.0, rtz);
-  TEST_FP_INT_OP_D(64,  fcvt.l.d, 0x01,          0, -0.9, rtz);
-  TEST_FP_INT_OP_D(65,  fcvt.l.d, 0x01,          0,  0.9, rtz);
-  TEST_FP_INT_OP_D(66,  fcvt.l.d, 0x00,          1,  1.0, rtz);
-  TEST_FP_INT_OP_D(67,  fcvt.l.d, 0x01,          1,  1.1, rtz);
-  TEST_FP_INT_OP_D(68,  fcvt.l.d, 0x00,-3000000000, -3e9, rtz);
-  TEST_FP_INT_OP_D(69,  fcvt.l.d, 0x00, 3000000000,  3e9, rtz);
-  TEST_FP_INT_OP_D(60,  fcvt.l.d, 0x10,     -1<<63,-3e19, rtz);
-  TEST_FP_INT_OP_D(61,  fcvt.l.d, 0x10,  (1<<63)-1, 3e19, rtz);
-
-  TEST_FP_INT_OP_D(72, fcvt.lu.d, 0x10,          0, -3.0, rtz);
-  TEST_FP_INT_OP_D(73, fcvt.lu.d, 0x10,          0, -1.0, rtz);
-  TEST_FP_INT_OP_D(74, fcvt.lu.d, 0x01,          0, -0.9, rtz);
-  TEST_FP_INT_OP_D(75, fcvt.lu.d, 0x01,          0,  0.9, rtz);
-  TEST_FP_INT_OP_D(76, fcvt.lu.d, 0x00,          1,  1.0, rtz);
-  TEST_FP_INT_OP_D(77, fcvt.lu.d, 0x01,          1,  1.1, rtz);
-  TEST_FP_INT_OP_D(78, fcvt.lu.d, 0x10,          0, -3e9, rtz);
-  TEST_FP_INT_OP_D(79, fcvt.lu.d, 0x00, 3000000000,  3e9, rtz);
-
   # test negative NaN, negative infinity conversion
-  TEST_CASE( 80, x1, 0x000000007fffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.w.s x1, f1)
-  TEST_CASE( 81, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.l.s x1, f1)
-  TEST_CASE( 82, x1, 0xffffffff80000000, la x1, tdat  ; flw f1,  8(x1); fcvt.w.s x1, f1)
-  TEST_CASE( 83, x1, 0x8000000000000000, la x1, tdat  ; flw f1,  8(x1); fcvt.l.s x1, f1)
-
-  TEST_CASE( 84, x1, 0x000000007fffffff, la x1, tdat_d; fld f1,  0(x1); fcvt.w.d x1, f1)
-  TEST_CASE( 85, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1,  0(x1); fcvt.l.d x1, f1)
-  TEST_CASE( 86, x1, 0xffffffff80000000, la x1, tdat_d; fld f1, 16(x1); fcvt.w.d x1, f1)
-  TEST_CASE( 87, x1, 0x8000000000000000, la x1, tdat_d; fld f1, 16(x1); fcvt.l.d x1, f1)
+  TEST_CASE( 42, x1, 0x000000007fffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.w.s x1, f1)
+  TEST_CASE( 43, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.l.s x1, f1)
+  TEST_CASE( 44, x1, 0xffffffff80000000, la x1, tdat  ; flw f1,  8(x1); fcvt.w.s x1, f1)
+  TEST_CASE( 45, x1, 0x8000000000000000, la x1, tdat  ; flw f1,  8(x1); fcvt.l.s x1, f1)
 
   # test positive NaN, positive infinity conversion
-  TEST_CASE( 88, x1, 0x000000007fffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.w.s x1, f1)
-  TEST_CASE( 89, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.l.s x1, f1)
-  TEST_CASE( 90, x1, 0x000000007fffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.w.s x1, f1)
-  TEST_CASE( 91, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.l.s x1, f1)
-
-  TEST_CASE( 92, x1, 0x000000007fffffff, la x1, tdat_d; fld f1,  8(x1); fcvt.w.d x1, f1)
-  TEST_CASE( 93, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1,  8(x1); fcvt.l.d x1, f1)
-  TEST_CASE( 94, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.w.d x1, f1)
-  TEST_CASE( 95, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.l.d x1, f1)
+  TEST_CASE( 52, x1, 0x000000007fffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.w.s x1, f1)
+  TEST_CASE( 53, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.l.s x1, f1)
+  TEST_CASE( 54, x1, 0x000000007fffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.w.s x1, f1)
+  TEST_CASE( 55, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.l.s x1, f1)
 
   # test NaN, infinity conversions to unsigned integer
-  TEST_CASE( 96, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.wu.s x1, f1)
-  TEST_CASE( 97, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.wu.s x1, f1)
-  TEST_CASE( 98, x1,                  0, la x1, tdat  ; flw f1,  8(x1); fcvt.wu.s x1, f1)
-  TEST_CASE( 99, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.wu.s x1, f1)
-  TEST_CASE(100, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.lu.s x1, f1)
-  TEST_CASE(101, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.lu.s x1, f1)
-  TEST_CASE(102, x1,                  0, la x1, tdat  ; flw f1,  8(x1); fcvt.lu.s x1, f1)
-  TEST_CASE(103, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.lu.s x1, f1)
+  TEST_CASE( 62, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.wu.s x1, f1)
+  TEST_CASE( 63, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.wu.s x1, f1)
+  TEST_CASE( 64, x1,                  0, la x1, tdat  ; flw f1,  8(x1); fcvt.wu.s x1, f1)
+  TEST_CASE( 65, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.wu.s x1, f1)
+  TEST_CASE( 66, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.lu.s x1, f1)
+  TEST_CASE( 67, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.lu.s x1, f1)
+  TEST_CASE( 68, x1,                  0, la x1, tdat  ; flw f1,  8(x1); fcvt.lu.s x1, f1)
+  TEST_CASE( 69, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.lu.s x1, f1)
    
-  TEST_CASE(104, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1,  0(x1); fcvt.wu.d x1, f1)
-  TEST_CASE(105, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1,  8(x1); fcvt.wu.d x1, f1)
-  TEST_CASE(106, x1,                  0, la x1, tdat_d; fld f1, 16(x1); fcvt.wu.d x1, f1)
-  TEST_CASE(107, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.wu.d x1, f1)
-  TEST_CASE(108, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1,  0(x1); fcvt.lu.d x1, f1)
-  TEST_CASE(109, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1,  8(x1); fcvt.lu.d x1, f1)
-  TEST_CASE(110, x1,                  0, la x1, tdat_d; fld f1, 16(x1); fcvt.lu.d x1, f1)
-  TEST_CASE(111, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.lu.d x1, f1)
-
   TEST_PASSFAIL
 
 RVTEST_CODE_END
diff --git a/isa/rv64uf/fdiv.S b/isa/rv64uf/fdiv.S
index 688f635..a75a23d 100644
--- a/isa/rv64uf/fdiv.S
+++ b/isa/rv64uf/fdiv.S
@@ -4,7 +4,7 @@
 # fdiv.S
 #-----------------------------------------------------------------------------
 #
-# Test f{div|sqrt}.{s|d} instructions.
+# Test f{div|sqrt}.s instructions.
 #
 
 #include "riscv_test.h"
@@ -17,27 +17,16 @@ RVTEST_CODE_BEGIN
   # Arithmetic tests
   #-------------------------------------------------------------
 
-  TEST_FP_OP2_S( 2,  fdiv.s, 1, 1.1557273520668288, 3.14159265, 2.71828182 );
-  TEST_FP_OP2_S( 3,  fdiv.s, 1,-0.9991093838555584,      -1234,     1235.1 );
-  TEST_FP_OP2_S( 4,  fdiv.s, 0,         3.14159265, 3.14159265,        1.0 );
+  TEST_FP_OP2_S(2,  fdiv.s, 1, 1.1557273520668288, 3.14159265, 2.71828182 );
+  TEST_FP_OP2_S(3,  fdiv.s, 1,-0.9991093838555584,      -1234,     1235.1 );
+  TEST_FP_OP2_S(4,  fdiv.s, 0,         3.14159265, 3.14159265,        1.0 );
 
-  TEST_FP_OP2_D( 5,  fdiv.d, 1, 1.1557273520668288, 3.14159265, 2.71828182 );
-  TEST_FP_OP2_D( 6,  fdiv.d, 1,-0.9991093838555584,      -1234,     1235.1 );
-  TEST_FP_OP2_D( 7,  fdiv.d, 0,         3.14159265, 3.14159265,        1.0 );
+  TEST_FP_OP1_S(5,  fsqrt.s, 1, 1.7724538498928541, 3.14159265 );
+  TEST_FP_OP1_S(6,  fsqrt.s, 0,                100,      10000 );
 
-  TEST_FP_OP1_S(11,  fsqrt.s, 1, 1.7724538498928541, 3.14159265 );
-  TEST_FP_OP1_S(12,  fsqrt.s, 0,                100,      10000 );
+  TEST_FP_OP1_S_DWORD_RESULT(7,  fsqrt.s, 0x10, 0x7FC00000, -1.0 );
 
-  TEST_FP_OP1_D(13,  fsqrt.d, 1, 1.7724538498928541, 3.14159265 );
-  TEST_FP_OP1_D(14,  fsqrt.d, 0,                100,      10000 );
-
-  TEST_FP_OP1_S_DWORD_RESULT(15,  fsqrt.s, 0x10,              0x7FC00000,      -1.0 );
-  TEST_FP_OP1_D_DWORD_RESULT(16,  fsqrt.d, 0x10,      0x7FF8000000000000,      -1.0 );
-
-  TEST_FP_OP1_S(17,  fsqrt.s, 1, 13.076696, 171.0);
-  TEST_FP_OP1_D(18,  fsqrt.d, 1, 13.076696830622021, 171.0);
-
-  TEST_FP_OP1_D(19,  fsqrt.d, 1,0.00040099251863345283320230749702, 1.60795e-7);
+  TEST_FP_OP1_S(8,  fsqrt.s, 1, 13.076696, 171.0);
 
   TEST_PASSFAIL
 
diff --git a/isa/rv64uf/fmadd.S b/isa/rv64uf/fmadd.S
index 62ea102..241bead 100644
--- a/isa/rv64uf/fmadd.S
+++ b/isa/rv64uf/fmadd.S
@@ -21,33 +21,17 @@ RVTEST_CODE_BEGIN
   TEST_FP_OP3_S( 3,  fmadd.s, 1,              1236.2, -1.0,    -1235.1,        1.1 );
   TEST_FP_OP3_S( 4,  fmadd.s, 0,               -12.0,  2.0,       -5.0,       -2.0 );
 
-  TEST_FP_OP3_D( 5,  fmadd.d, 0,                 3.5,  1.0,        2.5,        1.0 );
-  TEST_FP_OP3_D( 6,  fmadd.d, 1,  1236.1999999999999, -1.0,    -1235.1,        1.1 );
-  TEST_FP_OP3_D( 7,  fmadd.d, 0,               -12.0,  2.0,       -5.0,       -2.0 );
+  TEST_FP_OP3_S( 5, fnmadd.s, 0,                -3.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_S( 6, fnmadd.s, 1,             -1236.2, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_S( 7, fnmadd.s, 0,                12.0,  2.0,       -5.0,       -2.0 );
 
-  TEST_FP_OP3_S( 8, fnmadd.s, 0,                -3.5,  1.0,        2.5,        1.0 );
-  TEST_FP_OP3_S( 9, fnmadd.s, 1,             -1236.2, -1.0,    -1235.1,        1.1 );
-  TEST_FP_OP3_S(10, fnmadd.s, 0,                12.0,  2.0,       -5.0,       -2.0 );
+  TEST_FP_OP3_S( 8,  fmsub.s, 0,                 1.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_S( 9,  fmsub.s, 1,                1234, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_S(10,  fmsub.s, 0,                -8.0,  2.0,       -5.0,       -2.0 );
 
-  TEST_FP_OP3_D(11, fnmadd.d, 0,                -3.5,  1.0,        2.5,        1.0 );
-  TEST_FP_OP3_D(12, fnmadd.d, 1, -1236.1999999999999, -1.0,    -1235.1,        1.1 );
-  TEST_FP_OP3_D(13, fnmadd.d, 0,                12.0,  2.0,       -5.0,       -2.0 );
-
-  TEST_FP_OP3_S(14,  fmsub.s, 0,                 1.5,  1.0,        2.5,        1.0 );
-  TEST_FP_OP3_S(15,  fmsub.s, 1,                1234, -1.0,    -1235.1,        1.1 );
-  TEST_FP_OP3_S(16,  fmsub.s, 0,                -8.0,  2.0,       -5.0,       -2.0 );
-
-  TEST_FP_OP3_D(17,  fmsub.d, 0,                 1.5,  1.0,        2.5,        1.0 );
-  TEST_FP_OP3_D(18,  fmsub.d, 1,                1234, -1.0,    -1235.1,        1.1 );
-  TEST_FP_OP3_D(19,  fmsub.d, 0,                -8.0,  2.0,       -5.0,       -2.0 );
-
-  TEST_FP_OP3_S(20, fnmsub.s, 0,                -1.5,  1.0,        2.5,        1.0 );
-  TEST_FP_OP3_S(21, fnmsub.s, 1,               -1234, -1.0,    -1235.1,        1.1 );
-  TEST_FP_OP3_S(22, fnmsub.s, 0,                 8.0,  2.0,       -5.0,       -2.0 );
-
-  TEST_FP_OP3_D(23, fnmsub.d, 0,                -1.5,  1.0,        2.5,        1.0 );
-  TEST_FP_OP3_D(24, fnmsub.d, 1,               -1234, -1.0,    -1235.1,        1.1 );
-  TEST_FP_OP3_D(25, fnmsub.d, 0,                 8.0,  2.0,       -5.0,       -2.0 );
+  TEST_FP_OP3_S(11, fnmsub.s, 0,                -1.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_S(12, fnmsub.s, 1,               -1234, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_S(13, fnmsub.s, 0,                 8.0,  2.0,       -5.0,       -2.0 );
 
   TEST_PASSFAIL
 
diff --git a/isa/rv64uf/fmin.S b/isa/rv64uf/fmin.S
index 56a6e7b..a2650e5 100644
--- a/isa/rv64uf/fmin.S
+++ b/isa/rv64uf/fmin.S
@@ -4,7 +4,7 @@
 # fmin.S
 #-----------------------------------------------------------------------------
 #
-# Test f{min|max}.{s|d} instructinos.
+# Test f{min|max}.s instructinos.
 #
 
 #include "riscv_test.h"
@@ -31,20 +31,6 @@ RVTEST_CODE_BEGIN
   TEST_FP_OP2_S(16,  fmax.s, 0, 3.14159265, 3.14159265, 0.00000001 );
   TEST_FP_OP2_S(17,  fmax.s, 0,       -1.0,       -1.0,       -2.0 );
 
-  TEST_FP_OP2_D(22,  fmin.d, 0,        1.0,        2.5,        1.0 );
-  TEST_FP_OP2_D(23,  fmin.d, 0,    -1235.1,    -1235.1,        1.1 );
-  TEST_FP_OP2_D(24,  fmin.d, 0,    -1235.1,        1.1,    -1235.1 );
-  TEST_FP_OP2_D(25,  fmin.d, 0,    -1235.1,        NaN,    -1235.1 );
-  TEST_FP_OP2_D(26,  fmin.d, 0, 0.00000001, 3.14159265, 0.00000001 );
-  TEST_FP_OP2_D(27,  fmin.d, 0,       -2.0,       -1.0,       -2.0 );
-
-  TEST_FP_OP2_D(32,  fmax.d, 0,        2.5,        2.5,        1.0 );
-  TEST_FP_OP2_D(33,  fmax.d, 0,        1.1,    -1235.1,        1.1 );
-  TEST_FP_OP2_D(34,  fmax.d, 0,        1.1,        1.1,    -1235.1 );
-  TEST_FP_OP2_D(35,  fmax.d, 0,    -1235.1,        NaN,    -1235.1 );
-  TEST_FP_OP2_D(36,  fmax.d, 0, 3.14159265, 3.14159265, 0.00000001 );
-  TEST_FP_OP2_D(37,  fmax.d, 0,       -1.0,       -1.0,       -2.0 );
-
   TEST_PASSFAIL
 
 RVTEST_CODE_END
diff --git a/isa/rv64uf/fsgnj.S b/isa/rv64uf/fsgnj.S
index 68d5ee6..6d4bdb4 100644
--- a/isa/rv64uf/fsgnj.S
+++ b/isa/rv64uf/fsgnj.S
@@ -4,7 +4,7 @@
 # fsgnj.S
 #-----------------------------------------------------------------------------
 #
-# Test fsgn{j|jn|x}.{s|d} instructions.
+# Test fsgn{j|jn|x}.s instructions.
 #
 
 #include "riscv_test.h"
@@ -32,21 +32,6 @@ RVTEST_CODE_BEGIN
   TEST_FP_OP2_S(24, fsgnjx.s, 0,  8.3, -8.3, -3.0 );
   TEST_FP_OP2_S(25, fsgnjx.s, 0, -9.3, -9.3,  4.0 );
 
-  TEST_FP_OP2_D(32,  fsgnj.d, 0, -6.3,  6.3, -1.0 );
-  TEST_FP_OP2_D(33,  fsgnj.d, 0,  7.3,  7.3,  2.0 );
-  TEST_FP_OP2_D(34,  fsgnj.d, 0, -8.3, -8.3, -3.0 );
-  TEST_FP_OP2_D(35,  fsgnj.d, 0,  9.3, -9.3,  4.0 );
-
-  TEST_FP_OP2_D(42, fsgnjn.d, 0,  6.3,  6.3, -1.0 );
-  TEST_FP_OP2_D(43, fsgnjn.d, 0, -7.3,  7.3,  2.0 );
-  TEST_FP_OP2_D(44, fsgnjn.d, 0,  8.3, -8.3, -3.0 );
-  TEST_FP_OP2_D(45, fsgnjn.d, 0, -9.3, -9.3,  4.0 );
-
-  TEST_FP_OP2_D(52, fsgnjx.d, 0, -6.3,  6.3, -1.0 );
-  TEST_FP_OP2_D(53, fsgnjx.d, 0,  7.3,  7.3,  2.0 );
-  TEST_FP_OP2_D(54, fsgnjx.d, 0,  8.3, -8.3, -3.0 );
-  TEST_FP_OP2_D(55, fsgnjx.d, 0, -9.3, -9.3,  4.0 );
-
   TEST_PASSFAIL
 
 RVTEST_CODE_END
diff --git a/isa/rv64uf/ldst.S b/isa/rv64uf/ldst.S
index 63123f2..c35dd8d 100644
--- a/isa/rv64uf/ldst.S
+++ b/isa/rv64uf/ldst.S
@@ -15,8 +15,6 @@ RVTEST_CODE_BEGIN
 
   TEST_CASE(2, a0, 0x40000000deadbeef, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); ld a0, 16(a1))
   TEST_CASE(3, a0, 0x1337d00dbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); ld a0, 24(a1))
-  TEST_CASE(4, a0, 0x40000000bf800000, la a1, tdat; fld f2, 0(a1); fsd f2, 16(a1); ld a0, 16(a1))
-  TEST_CASE(5, a0, 0xc080000040400000, la a1, tdat; fld f2, 8(a1); fsd f2, 16(a1); ld a0, 16(a1))
 
   TEST_PASSFAIL
 
diff --git a/isa/rv64uf/move.S b/isa/rv64uf/move.S
index 53b8cf3..a94af55 100644
--- a/isa/rv64uf/move.S
+++ b/isa/rv64uf/move.S
@@ -5,7 +5,7 @@
 #-----------------------------------------------------------------------------
 #
 # This test verifies that mxtf.[s,d], mftx.[s,d], fssr, frsr,
-# and fsgnj[x|n].[s|d] work properly.
+# and fsgnj[x|n].s work properly.
 #
 
 #include "riscv_test.h"
@@ -22,12 +22,10 @@ fssr a0
   TEST_CASE(4, a0, 0x34, frsr a0)
 
   TEST_CASE(5, a0, 0xFFFFFFFFBF812345, li a1, 0xFFFFFFFFBF812345; fmv.s.x f0, a1; fmv.x.s a0, f0)
-  TEST_CASE(6, a0, 0x3FF02468A0000000, li a1, 0x3FF02468A0000000; fmv.d.x f1, a1; fmv.x.d a0, f1)
 
-  TEST_CASE(7, a0, 0xFFFFFFFFBF812345, li a1, 0xFFFFFFFFBF812345; fmv.s.x f0, a1; fsgnj.s f1, f0, f0; fmv.x.s a0, f1)
-  TEST_CASE(8, a0, 0x000000004BA98765, li a1, 0xFFFFFFFFCBA98765; fmv.s.x f0, a1; fsgnjx.s f1, f0, f0; fmv.x.s a0, f1)
-  TEST_CASE(9, a0, 0x000000005EADBEEF, li a1, 0xFFFFFFFFDEADBEEF; fmv.s.x f0, a1; fsgnjn.s f1, f0, f0; fmv.x.s a0, f1)
-  TEST_CASE(10, a0, 0xBFF02468A0001000, li a1, 0x3FF02468A0001000; li a2, -1; fmv.d.x f1, a1; fmv.d.x f2, a2; fsgnj.d f0, f1, f2; fmv.x.d a0, f0)
+  TEST_CASE(6, a0, 0xFFFFFFFFBF812345, li a1, 0xFFFFFFFFBF812345; fmv.s.x f0, a1; fsgnj.s f1, f0, f0; fmv.x.s a0, f1)
+  TEST_CASE(7, a0, 0x000000004BA98765, li a1, 0xFFFFFFFFCBA98765; fmv.s.x f0, a1; fsgnjx.s f1, f0, f0; fmv.x.s a0, f1)
+  TEST_CASE(8, a0, 0x000000005EADBEEF, li a1, 0xFFFFFFFFDEADBEEF; fmv.s.x f0, a1; fsgnjn.s f1, f0, f0; fmv.x.s a0, f1)
 
   TEST_PASSFAIL
 
diff --git a/isa/rv64uf/recoding.S b/isa/rv64uf/recoding.S
index 2ab17e2..802be66 100644
--- a/isa/rv64uf/recoding.S
+++ b/isa/rv64uf/recoding.S
@@ -25,31 +25,13 @@ RVTEST_CODE_BEGIN
   TEST_CASE( 4, a0, 0, flt.s a0, f0, f1)
 
   # Likewise, but for zeroes.
-  fcvt.d.w f0, x0
+  fcvt.s.w f0, x0
   li a0, 1
-  fcvt.d.w f1, a0
-  fmul.d f1, f1, f0
-  TEST_CASE(5, a0, 1, feq.d a0, f0, f1)
-  TEST_CASE(6, a0, 1, fle.d a0, f0, f1)
-  TEST_CASE(7, a0, 0, flt.d a0, f0, f1)
-
-  # When converting small doubles to single-precision subnormals,
-  # ensure that the extra precision is discarded.
-  flw f0, big, a0
-  fld f1, tiny, a0
-  fcvt.s.d f1, f1
-  fmul.s f0, f0, f1
-  fmv.x.s a0, f0
-  lw a1, small
-  TEST_CASE(10, a0, 0, sub a0, a0, a1)
-
-  # Make sure FSD+FLD correctly saves and restores a single-precision value.
-  flw f0, three, a0
-  fadd.s f1, f0, f0
-  fadd.s f0, f0, f0
-  fsd f0, tiny, a0
-  fld f0, tiny, a0
-  TEST_CASE(20, a0, 1, feq.s a0, f0, f1)
+  fcvt.s.w f1, a0
+  fmul.s f1, f1, f0
+  TEST_CASE(5, a0, 1, feq.s a0, f0, f1)
+  TEST_CASE(6, a0, 1, fle.s a0, f0, f1)
+  TEST_CASE(7, a0, 0, flt.s a0, f0, f1)
 
   TEST_PASSFAIL
 
@@ -60,8 +42,5 @@ RVTEST_DATA_BEGIN
 
 minf: .float -Inf
 three: .float 3.0
-big: .float 1221
-small: .float 2.9133121e-37
-tiny: .double 2.3860049081905093e-40
 
 RVTEST_DATA_END
diff --git a/isa/rv64ui/Makefrag b/isa/rv64ui/Makefrag
index 4af2504..7920b99 100644
--- a/isa/rv64ui/Makefrag
+++ b/isa/rv64ui/Makefrag
@@ -4,21 +4,15 @@
 
 rv64ui_sc_tests = \
 	add addi addiw addw \
-	amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \
-	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
-	lrsc \
 	and andi \
 	auipc \
 	beq bge bgeu blt bltu bne \
-	div divu divuw divw \
 	example simple \
 	fence_i \
 	j jal jalr \
 	lb lbu lh lhu lw lwu ld \
 	lui \
-	mul mulh mulhsu mulhu mulw \
 	or ori \
-	rem remu remuw remw \
 	sb sh sw sd \
 	sll slli slliw sllw \
 	slt slti sltiu sltu \
diff --git a/isa/rv64um/Makefrag b/isa/rv64um/Makefrag
new file mode 100644
index 0000000..360bd7a
--- /dev/null
+++ b/isa/rv64um/Makefrag
@@ -0,0 +1,13 @@
+#=======================================================================
+# Makefrag for rv64um tests
+#-----------------------------------------------------------------------
+
+rv64um_sc_tests = \
+	div divu divuw divw \
+	mul mulh mulhsu mulhu mulw \
+	rem remu remuw remw \
+
+rv64um_p_tests = $(addprefix rv64um-p-, $(rv64um_sc_tests))
+rv64um_v_tests = $(addprefix rv64um-v-, $(rv64um_sc_tests))
+
+spike_tests += $(rv64um_p_tests) $(rv64um_v_tests)
diff --git a/isa/rv64ui/div.S b/isa/rv64um/div.S
index ee21f0c..ee21f0c 100644
--- a/isa/rv64ui/div.S
+++ b/isa/rv64um/div.S
diff --git a/isa/rv64ui/divu.S b/isa/rv64um/divu.S
index e63fd65..e63fd65 100644
--- a/isa/rv64ui/divu.S
+++ b/isa/rv64um/divu.S
diff --git a/isa/rv64ui/divuw.S b/isa/rv64um/divuw.S
index 4c9eee7..4c9eee7 100644
--- a/isa/rv64ui/divuw.S
+++ b/isa/rv64um/divuw.S
diff --git a/isa/rv64ui/divw.S b/isa/rv64um/divw.S
index 4cffa1a..4cffa1a 100644
--- a/isa/rv64ui/divw.S
+++ b/isa/rv64um/divw.S
diff --git a/isa/rv64ui/mul.S b/isa/rv64um/mul.S
index c647e97..c647e97 100644
--- a/isa/rv64ui/mul.S
+++ b/isa/rv64um/mul.S
diff --git a/isa/rv64ui/mulh.S b/isa/rv64um/mulh.S
index 1fd12a1..1fd12a1 100644
--- a/isa/rv64ui/mulh.S
+++ b/isa/rv64um/mulh.S
diff --git a/isa/rv64ui/mulhsu.S b/isa/rv64um/mulhsu.S
index c037db2..c037db2 100644
--- a/isa/rv64ui/mulhsu.S
+++ b/isa/rv64um/mulhsu.S
diff --git a/isa/rv64ui/mulhu.S b/isa/rv64um/mulhu.S
index aa7b762..aa7b762 100644
--- a/isa/rv64ui/mulhu.S
+++ b/isa/rv64um/mulhu.S
diff --git a/isa/rv64ui/mulw.S b/isa/rv64um/mulw.S
index 379c3f2..379c3f2 100644
--- a/isa/rv64ui/mulw.S
+++ b/isa/rv64um/mulw.S
diff --git a/isa/rv64ui/rem.S b/isa/rv64um/rem.S
index e3248ff..e3248ff 100644
--- a/isa/rv64ui/rem.S
+++ b/isa/rv64um/rem.S
diff --git a/isa/rv64ui/remu.S b/isa/rv64um/remu.S
index 6946d0d..6946d0d 100644
--- a/isa/rv64ui/remu.S
+++ b/isa/rv64um/remu.S
diff --git a/isa/rv64ui/remuw.S b/isa/rv64um/remuw.S
index 334b5c5..334b5c5 100644
--- a/isa/rv64ui/remuw.S
+++ b/isa/rv64um/remuw.S
diff --git a/isa/rv64ui/remw.S b/isa/rv64um/remw.S
index 3ae8e3d..3ae8e3d 100644
--- a/isa/rv64ui/remw.S
+++ b/isa/rv64um/remw.S