aboutsummaryrefslogtreecommitdiff
path: root/isa/rv64ui
diff options
context:
space:
mode:
authorAndrew Waterman <waterman@eecs.berkeley.edu>2014-01-16 00:12:38 -0800
committerAndrew Waterman <waterman@eecs.berkeley.edu>2014-01-16 00:12:38 -0800
commitd710b4ba5d3405a338d133f77f5d19bd12a4e8b7 (patch)
tree3eefaa68b9bc397c600e642a88fd53848dec6a5e /isa/rv64ui
parentf9d44cfc5d48f1bb21ef5910da3e3dfbba7de075 (diff)
downloadriscv-tests-d710b4ba5d3405a338d133f77f5d19bd12a4e8b7.zip
riscv-tests-d710b4ba5d3405a338d133f77f5d19bd12a4e8b7.tar.gz
riscv-tests-d710b4ba5d3405a338d133f77f5d19bd12a4e8b7.tar.bz2
Make LR/SC test more thorough
Diffstat (limited to 'isa/rv64ui')
-rw-r--r--isa/rv64ui/lrsc.S51
1 files changed, 32 insertions, 19 deletions
diff --git a/isa/rv64ui/lrsc.S b/isa/rv64ui/lrsc.S
index ec6748c..b3544f4 100644
--- a/isa/rv64ui/lrsc.S
+++ b/isa/rv64ui/lrsc.S
@@ -11,43 +11,56 @@
RVTEST_RV64U
RVTEST_CODE_BEGIN
-# wait for all cores ao boot
+# wait for all cores to boot
la a0, coreid
li a1, 1
-amoadd.w a2, a1, 0(a0)
+amoadd.w a2, a1, (a0)
lw a3, 4(x0)
-1: lw a1, 0(a0)
+1: lw a1, (a0)
blt a1, a3, 1b
-# have each core add its coreid ao foo 1000 aimes
+# make sure that sc without a reservation fails.
+TEST_CASE( 2, a4, 1, \
+ la a0, foo; \
+ sc.w a4, x0, (a0); \
+)
+
+# make sure that sc with the wrong reservation fails.
+TEST_CASE( 3, a4, 1, \
+ la a0, foo; \
+ add a1, a0, 1024; \
+ lr.w a1, (a1); \
+ sc.w a4, a1, (a0); \
+)
+
+# have each core add its coreid to foo 1000 times
la a0, foo
li a1, 1000
-1: lr.w a4, 0(a0)
-#amoadd.w x0, a2, 0(a0)
+1: lr.w a4, (a0)
add a4, a4, a2
-sc.w a4, a4, 0(a0)
+sc.w a4, a4, (a0)
bnez a4, 1b
add a1, a1, -1
bnez a1, 1b
-# wait for all cores ao finish
+# wait for all cores to finish
la a0, barrier
li a1, 1
-amoadd.w x0, a1, 0(a0)
-1: lw a1, 0(a0)
+amoadd.w x0, a1, (a0)
+1: lw a1, (a0)
blt a1, a3, 1b
fence
# expected result is 1000*ncores*(ncores-1)/2
-la a0, foo
-li a1, 500
-mul a1, a1, a3
-add a2, a3, -1
-mul a1, a1, a2
-lw a2, 0(a0)
-bne a2, a1, 1f
-RVTEST_PASS
-1: RVTEST_FAIL
+TEST_CASE( 4, a2, 0, \
+ la a0, foo; \
+ li a1, 500; \
+ mul a1, a1, a3; \
+ add a2, a3, -1; \
+ mul a1, a1, a2; \
+ lw a2, (a0); \
+ sub a2, a2, a1; \
+)
TEST_PASSFAIL