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authorTorbjørn <tovine@users.noreply.github.com>2017-11-27 06:56:53 +0100
committerAndrew Waterman <aswaterman@gmail.com>2017-11-26 21:56:53 -0800
commit49f478416cec9f73801fdc5dedf9955494be8c66 (patch)
treeee07276de133354d01ba5efbf02514e2e841b25f /isa/rv64ud
parent018aea17aca9abb6221e1a59d943ecdd386cc8ec (diff)
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Rv32ud tests (#108)
* Probably implemented the changes required to support fadd test for rv32ud * Created test files in rv32ud, implemented working(?) test for ldst * fclass, fcvt_w, fmin and recoding seem to be working now * Got fdiv (and sqrt) tests working * fmadd tests seem to work * fcmp works * [WIP] fcvt working, but lacks a 32-bit implementation of the final test * Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST * Added Makefrag for rv32ud tests and included in main isa Makefile * Don't run 64-bit tests if the defined XLEN is 32
Diffstat (limited to 'isa/rv64ud')
-rw-r--r--isa/rv64ud/fadd.S6
-rw-r--r--isa/rv64ud/fclass.S6
-rw-r--r--isa/rv64ud/fcmp.S6
-rw-r--r--isa/rv64ud/fcvt.S23
-rw-r--r--isa/rv64ud/fcvt_w.S12
-rw-r--r--isa/rv64ud/fdiv.S12
-rw-r--r--isa/rv64ud/fmadd.S6
-rw-r--r--isa/rv64ud/fmin.S6
-rw-r--r--isa/rv64ud/move.S1
9 files changed, 78 insertions, 0 deletions
diff --git a/isa/rv64ud/fadd.S b/isa/rv64ud/fadd.S
index 71e7f82..51ca82d 100644
--- a/isa/rv64ud/fadd.S
+++ b/isa/rv64ud/fadd.S
@@ -13,6 +13,12 @@
RVTEST_RV64UF
RVTEST_CODE_BEGIN
+#if __riscv_xlen == 32
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_FP_OP2_D
+ #define TEST_FP_OP2_D TEST_FP_OP2_D32
+#endif
+
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
diff --git a/isa/rv64ud/fclass.S b/isa/rv64ud/fclass.S
index 3939490..04a8947 100644
--- a/isa/rv64ud/fclass.S
+++ b/isa/rv64ud/fclass.S
@@ -13,6 +13,12 @@
RVTEST_RV64UF
RVTEST_CODE_BEGIN
+#if __riscv_xlen == 32
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_FCLASS_D
+ #define TEST_FCLASS_D TEST_FCLASS_D32
+#endif
+
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
diff --git a/isa/rv64ud/fcmp.S b/isa/rv64ud/fcmp.S
index 39e6023..7727a28 100644
--- a/isa/rv64ud/fcmp.S
+++ b/isa/rv64ud/fcmp.S
@@ -17,6 +17,12 @@ RVTEST_CODE_BEGIN
# Arithmetic tests
#-------------------------------------------------------------
+#if __riscv_xlen == 32
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_FP_CMP_OP_D
+ #define TEST_FP_CMP_OP_D TEST_FP_CMP_OP_D32
+#endif
+
TEST_FP_CMP_OP_D( 2, feq.d, 0x00, 1, -1.36, -1.36)
TEST_FP_CMP_OP_D( 3, fle.d, 0x00, 1, -1.36, -1.36)
TEST_FP_CMP_OP_D( 4, flt.d, 0x00, 0, -1.36, -1.36)
diff --git a/isa/rv64ud/fcvt.S b/isa/rv64ud/fcvt.S
index 4f25d07..98916b1 100644
--- a/isa/rv64ud/fcvt.S
+++ b/isa/rv64ud/fcvt.S
@@ -13,6 +13,15 @@
RVTEST_RV64UF
RVTEST_CODE_BEGIN
+#if __riscv_xlen == 32
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_INT_FP_OP_D
+ #define TEST_INT_FP_OP_D TEST_INT_FP_OP_D32
+
+ #undef TEST_FCVT_S_D
+ #define TEST_FCVT_S_D TEST_FCVT_S_D32
+#endif
+
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
@@ -23,15 +32,18 @@ RVTEST_CODE_BEGIN
TEST_INT_FP_OP_D(4, fcvt.d.wu, 2.0, 2);
TEST_INT_FP_OP_D(5, fcvt.d.wu, 4294967294, -2);
+#if __riscv_xlen >= 64
TEST_INT_FP_OP_D(6, fcvt.d.l, 2.0, 2);
TEST_INT_FP_OP_D(7, fcvt.d.l, -2.0, -2);
TEST_INT_FP_OP_D(8, fcvt.d.lu, 2.0, 2);
TEST_INT_FP_OP_D(9, fcvt.d.lu, 1.8446744073709552e19, -2);
+#endif
TEST_FCVT_S_D(10, -1.5, -1.5)
TEST_FCVT_D_S(11, -1.5, -1.5)
+#if __riscv_xlen >= 64
TEST_CASE(12, a0, 0x7ff8000000000000,
la a1, test_data_22;
ld a2, 0(a1);
@@ -40,6 +52,17 @@ RVTEST_CODE_BEGIN
fcvt.d.s f2, f2;
fmv.x.d a0, f2;
)
+#else
+ TEST_CASE_D32(12, a0, a1, 0x7ff8000000000000,
+ la a1, test_data_22;
+ fld f2, 0(a1);
+ fcvt.s.d f2, f2;
+ fcvt.d.s f2, f2;
+ fsd f2, 0(a1);
+ lw a0, 0(a1);
+ lw a1, 4(a1)
+ )
+#endif
TEST_PASSFAIL
diff --git a/isa/rv64ud/fcvt_w.S b/isa/rv64ud/fcvt_w.S
index 50e794c..56cc29d 100644
--- a/isa/rv64ud/fcvt_w.S
+++ b/isa/rv64ud/fcvt_w.S
@@ -35,6 +35,7 @@ RVTEST_CODE_BEGIN
TEST_FP_INT_OP_D(18, fcvt.wu.d, 0x10, 0, -3e9, rtz);
TEST_FP_INT_OP_D(19, fcvt.wu.d, 0x00, 0xffffffffb2d05e00, 3e9, rtz);
+#if __riscv_xlen >= 64
TEST_FP_INT_OP_D(22, fcvt.l.d, 0x01, -1, -1.1, rtz);
TEST_FP_INT_OP_D(23, fcvt.l.d, 0x00, -1, -1.0, rtz);
TEST_FP_INT_OP_D(24, fcvt.l.d, 0x01, 0, -0.9, rtz);
@@ -54,28 +55,39 @@ RVTEST_CODE_BEGIN
TEST_FP_INT_OP_D(37, fcvt.lu.d, 0x01, 1, 1.1, rtz);
TEST_FP_INT_OP_D(38, fcvt.lu.d, 0x10, 0, -3e9, rtz);
TEST_FP_INT_OP_D(39, fcvt.lu.d, 0x00, 3000000000, 3e9, rtz);
+#endif
# test negative NaN, negative infinity conversion
TEST_CASE(42, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.w.d x1, f1)
+#if __riscv_xlen >= 64
TEST_CASE(43, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.l.d x1, f1)
+#endif
TEST_CASE(44, x1, 0xffffffff80000000, la x1, tdat_d; fld f1, 16(x1); fcvt.w.d x1, f1)
+#if __riscv_xlen >= 64
TEST_CASE(45, x1, 0x8000000000000000, la x1, tdat_d; fld f1, 16(x1); fcvt.l.d x1, f1)
+#endif
# test positive NaN, positive infinity conversion
TEST_CASE(52, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.w.d x1, f1)
+#if __riscv_xlen >= 64
TEST_CASE(53, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.l.d x1, f1)
+#endif
TEST_CASE(54, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.w.d x1, f1)
+#if __riscv_xlen >= 64
TEST_CASE(55, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.l.d x1, f1)
+#endif
# test NaN, infinity conversions to unsigned integer
TEST_CASE(62, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.wu.d x1, f1)
TEST_CASE(63, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.wu.d x1, f1)
TEST_CASE(64, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.wu.d x1, f1)
TEST_CASE(65, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.wu.d x1, f1)
+#if __riscv_xlen >= 64
TEST_CASE(66, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.lu.d x1, f1)
TEST_CASE(67, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.lu.d x1, f1)
TEST_CASE(68, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.lu.d x1, f1)
TEST_CASE(69, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.lu.d x1, f1)
+#endif
TEST_PASSFAIL
diff --git a/isa/rv64ud/fdiv.S b/isa/rv64ud/fdiv.S
index 8a9fd4d..f985fa1 100644
--- a/isa/rv64ud/fdiv.S
+++ b/isa/rv64ud/fdiv.S
@@ -13,6 +13,18 @@
RVTEST_RV64UF
RVTEST_CODE_BEGIN
+#if __riscv_xlen == 32
+ # Replace the functions with the 32-bit variants defined in test_macros.h
+ #undef TEST_FP_OP2_D
+ #define TEST_FP_OP2_D TEST_FP_OP2_D32
+
+ #undef TEST_FP_OP1_D
+ #define TEST_FP_OP1_D TEST_FP_OP1_D32
+
+ #undef TEST_FP_OP1_D_DWORD_RESULT
+ #define TEST_FP_OP1_D_DWORD_RESULT TEST_FP_OP1_D32_DWORD_RESULT
+#endif
+
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
diff --git a/isa/rv64ud/fmadd.S b/isa/rv64ud/fmadd.S
index 7a69aad..1e3ba66 100644
--- a/isa/rv64ud/fmadd.S
+++ b/isa/rv64ud/fmadd.S
@@ -13,6 +13,12 @@
RVTEST_RV64UF
RVTEST_CODE_BEGIN
+#if __riscv_xlen == 32
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_FP_OP3_D
+ #define TEST_FP_OP3_D TEST_FP_OP3_D32
+#endif
+
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
diff --git a/isa/rv64ud/fmin.S b/isa/rv64ud/fmin.S
index 55df33d..10ff8e6 100644
--- a/isa/rv64ud/fmin.S
+++ b/isa/rv64ud/fmin.S
@@ -13,6 +13,12 @@
RVTEST_RV64UF
RVTEST_CODE_BEGIN
+#if __riscv_xlen == 32
+ # Replace the function with the 32-bit variant defined in test_macros.h
+ #undef TEST_FP_OP2_D
+ #define TEST_FP_OP2_D TEST_FP_OP2_D32
+#endif
+
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
diff --git a/isa/rv64ud/move.S b/isa/rv64ud/move.S
index ccc41b5..8911d95 100644
--- a/isa/rv64ud/move.S
+++ b/isa/rv64ud/move.S
@@ -13,6 +13,7 @@
RVTEST_RV64UF
RVTEST_CODE_BEGIN
+#TODO: make 32-bit compatible version
#define TEST_FSGNJD(n, insn, new_sign, rs1_sign, rs2_sign) \
TEST_CASE(n, a0, 0x123456789abcdef0 | (-(new_sign) << 63), \
li a1, ((rs1_sign) << 63) | 0x123456789abcdef0; \
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