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| author | Andrew Waterman <andrew@sifive.com> | 2018-07-09 14:25:46 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-07-09 14:27:36 -0700 |
| commit | 294bfce8a1ca2fc501b8939292146e44f813a2b8 (patch) | |
| tree | f9f9bd2d0c5f945766dcc7f9c28b331d52c8b2c9 /isa/rv64ua | |
| parent | 8519aa3f0ccf4032249b346fbd67855da99b5f3c (diff) | |
| download | riscv-tests-294bfce8a1ca2fc501b8939292146e44f813a2b8.zip riscv-tests-294bfce8a1ca2fc501b8939292146e44f813a2b8.tar.gz riscv-tests-294bfce8a1ca2fc501b8939292146e44f813a2b8.tar.bz2 | |
Check that SC yields the load reservation
https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612
Diffstat (limited to 'isa/rv64ua')
| -rw-r--r-- | isa/rv64ua/lrsc.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/isa/rv64ua/lrsc.S b/isa/rv64ua/lrsc.S index 14ef07d..f73a404 100644 --- a/isa/rv64ua/lrsc.S +++ b/isa/rv64ua/lrsc.S @@ -70,6 +70,15 @@ TEST_CASE( 4, a0, 0, \ bgez a3, 1b ) +# make sure that sc-after-successful-sc fails. +TEST_CASE( 5, a1, 1, \ + la a0, foo; \ +1:lr.w a1, (a0); \ + sc.w a1, x0, (a0); \ + bnez a1, 1b; \ + sc.w a1, x0, (a0) +) + TEST_PASSFAIL RVTEST_CODE_END |