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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-09 12:43:36 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-09 12:43:36 -0800 |
| commit | fa02d39baff17799670a15975388c8e563c1a780 (patch) | |
| tree | f71c2e3679b1797146a714325e0745af0b8307d1 /isa/rv64si/dirty.S | |
| parent | 7f5d59f657b25bdd5bebdc6c8875c8cd629dd330 (diff) | |
| download | riscv-tests-fa02d39baff17799670a15975388c8e563c1a780.zip riscv-tests-fa02d39baff17799670a15975388c8e563c1a780.tar.gz riscv-tests-fa02d39baff17799670a15975388c8e563c1a780.tar.bz2 | |
Permit flexible dirty-bit behavior
Diffstat (limited to 'isa/rv64si/dirty.S')
| -rw-r--r-- | isa/rv64si/dirty.S | 42 |
1 files changed, 26 insertions, 16 deletions
diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S index 0314cf5..e3a7987 100644 --- a/isa/rv64si/dirty.S +++ b/isa/rv64si/dirty.S @@ -14,13 +14,16 @@ RVTEST_RV64M RVTEST_CODE_BEGIN # Turn on VM with superpage identity mapping + li a0, (SPTBR_MODE & ~(SPTBR_MODE<<1)) * SPTBR_MODE_SV39 la a1, page_table_1 srl a1, a1, RISCV_PGSHIFT + or a1, a1, a0 la a2, page_table_2 srl a2, a2, RISCV_PGSHIFT + or a2, a2, a0 csrw sptbr, a1 - sfence.vm - li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV39) | ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) + sfence.vma + li a1, (MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S csrs mstatus, a1 la a1, 1f - DRAM_BASE csrw mepc, a1 @@ -37,12 +40,12 @@ RVTEST_CODE_BEGIN # Load new page table li TESTNUM, 3 csrw sptbr, a2 - sfence.vm + sfence.vma # Try a non-faulting store to make sure dirty bit is set sw t0, dummy, t1 - # Make sure R and D bits are set + # Make sure D bit is set lw t0, page_table_2 li t1, PTE_A | PTE_D and t0, t0, t1 @@ -55,25 +58,32 @@ RVTEST_CODE_BEGIN .align 2 stvec_handler: csrr t0, scause + add t0, t0, -CAUSE_FAULT_STORE + bnez t0, die + li t1, 2 bne TESTNUM, t1, 1f - # Make sure R bit is set - lw t0, page_table_1 - li t1, PTE_A - and t0, t0, t1 - bne t0, t1, die - # Make sure D bit is clear lw t0, page_table_1 - li t1, PTE_D - and t0, t0, t1 - beq t0, t1, die - + and t1, t0, PTE_D + bnez t1, die +skip: csrr t0, sepc add t0, t0, 4 csrw sepc, t0 sret +1: + li t1, 3 + bne TESTNUM, t1, 1f + # The implementation doesn't appear to set D bits in HW. Skip the test, + # after making sure the D bit is clear. + lw t0, page_table_2 + and t1, t0, PTE_D + bnez t1, die + j pass + +1: die: RVTEST_FAIL @@ -85,9 +95,9 @@ RVTEST_DATA_BEGIN TEST_DATA .align 12 -page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X +page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_A dummy: .dword 0 .align 12 -page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_W +page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_W | PTE_A RVTEST_DATA_END |