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author | Andrew Waterman <andrew@sifive.com> | 2024-02-18 20:09:30 -0800 |
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committer | GitHub <noreply@github.com> | 2024-02-18 20:09:30 -0800 |
commit | 3bd02c8ab45666cf1c0532294f115c4d2ce3e027 (patch) | |
tree | 1a5653d944c240bb81dbfa4c37e922186af35215 /isa/rv32uzbs/bext.S | |
parent | ad33ed3cb50b4cc23a44657a541f76325e659af0 (diff) | |
parent | 9c06101326cdd451a051bc3e6469b3c76f24d101 (diff) | |
download | riscv-tests-3bd02c8ab45666cf1c0532294f115c4d2ce3e027.zip riscv-tests-3bd02c8ab45666cf1c0532294f115c4d2ce3e027.tar.gz riscv-tests-3bd02c8ab45666cf1c0532294f115c4d2ce3e027.tar.bz2 |
Merge pull request #539 from rogerchang23424/bitmanip
Add bitmanip test cases
Diffstat (limited to 'isa/rv32uzbs/bext.S')
-rw-r--r-- | isa/rv32uzbs/bext.S | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/isa/rv32uzbs/bext.S b/isa/rv32uzbs/bext.S new file mode 100644 index 0000000..0f838e5 --- /dev/null +++ b/isa/rv32uzbs/bext.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bext.S" |