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| author | Andrew Waterman <andrew@sifive.com> | 2024-02-18 20:09:30 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-02-18 20:09:30 -0800 |
| commit | 3bd02c8ab45666cf1c0532294f115c4d2ce3e027 (patch) | |
| tree | 1a5653d944c240bb81dbfa4c37e922186af35215 /isa/rv32uzbb/orc_b.S | |
| parent | ad33ed3cb50b4cc23a44657a541f76325e659af0 (diff) | |
| parent | 9c06101326cdd451a051bc3e6469b3c76f24d101 (diff) | |
| download | riscv-tests-3bd02c8ab45666cf1c0532294f115c4d2ce3e027.zip riscv-tests-3bd02c8ab45666cf1c0532294f115c4d2ce3e027.tar.gz riscv-tests-3bd02c8ab45666cf1c0532294f115c4d2ce3e027.tar.bz2 | |
Merge pull request #539 from rogerchang23424/bitmanip
Add bitmanip test cases
Diffstat (limited to 'isa/rv32uzbb/orc_b.S')
| -rw-r--r-- | isa/rv32uzbb/orc_b.S | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/isa/rv32uzbb/orc_b.S b/isa/rv32uzbb/orc_b.S new file mode 100644 index 0000000..7fb8441 --- /dev/null +++ b/isa/rv32uzbb/orc_b.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# orc.b.S +#----------------------------------------------------------------------------- +# +# Test orc.b instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, orc.b, 0x00000000, 0x00000000); + TEST_R_OP( 3, orc.b, 0x000000ff, 0x00000001); + TEST_R_OP( 4, orc.b, 0x000000ff, 0x00000003); + + TEST_R_OP( 5, orc.b, 0xffffff00, 0xffff8000 ); + TEST_R_OP( 6, orc.b, 0x00ff0000, 0x00800000 ); + TEST_R_OP( 7, orc.b, 0xffffff00, 0xffff8000 ); + + TEST_R_OP( 8, orc.b, 0x0000ffff, 0x00007fff); + TEST_R_OP( 9, orc.b, 0xffffffff, 0x7fffffff); + TEST_R_OP( 10, orc.b, 0x00ffffff, 0x0007ffff ); + + TEST_R_OP( 11, orc.b, 0xff000000, 0x80000000); + TEST_R_OP( 12, orc.b, 0xffffff00, 0x121f5000); + + TEST_R_OP( 13, orc.b, 0x00000000, 0x00000000); + TEST_R_OP( 14, orc.b, 0x000000ff, 0x0000000e); + TEST_R_OP( 15, orc.b, 0xffffffff, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, orc.b, 0xff, 13); + TEST_R_SRC1_EQ_DEST( 17, orc.b, 0xff, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, orc.b, 0xff, 13); + TEST_R_DEST_BYPASS( 29, 1, orc.b, 0xff, 19); + TEST_R_DEST_BYPASS( 20, 2, orc.b, 0xff, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, orc.b, 0x00ffff00, 0x007f8000 ); + TEST_R_OP( 22, orc.b, 0x00ffff00, 0x00808000 ); + TEST_R_OP( 23, orc.b, 0xffffff00, 0x01808000 ); + + TEST_R_OP( 24, orc.b, 0x0000ffff, 0x00007fff); + TEST_R_OP( 25, orc.b, 0xffffffff, 0x7fffffff); + TEST_R_OP( 26, orc.b, 0x00ffffff, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END |