Add rv32uf tests

13 files changed, 127 insertions, 0 deletions

diff --git a/isa/rv32uf/Makefrag b/isa/rv32uf/Makefrag
new file mode 100644
index 0000000..bc958a7
--- /dev/null
+++ b/isa/rv32uf/Makefrag
@@ -0,0 +1,12 @@
+#=======================================================================
+# Makefrag for rv32uf tests
+#-----------------------------------------------------------------------
+
+rv32uf_sc_tests = \
+	fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin fsgnj \
+	ldst move recoding \
+
+rv32uf_p_tests = $(addprefix rv32uf-p-, $(rv32uf_sc_tests))
+rv32uf_v_tests = $(addprefix rv32uf-v-, $(rv32uf_sc_tests))
+
+spike32_tests += $(rv32uf_p_tests) $(rv32uf_v_tests)
diff --git a/isa/rv32uf/fadd.S b/isa/rv32uf/fadd.S
new file mode 100644
index 0000000..b832c3d
--- /dev/null
+++ b/isa/rv32uf/fadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fadd.S"
diff --git a/isa/rv32uf/fclass.S b/isa/rv32uf/fclass.S
new file mode 100644
index 0000000..19bbcc5
--- /dev/null
+++ b/isa/rv32uf/fclass.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fclass.S"
diff --git a/isa/rv32uf/fcmp.S b/isa/rv32uf/fcmp.S
new file mode 100644
index 0000000..2dbf451
--- /dev/null
+++ b/isa/rv32uf/fcmp.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fcmp.S"
diff --git a/isa/rv32uf/fcvt.S b/isa/rv32uf/fcvt.S
new file mode 100644
index 0000000..627f1f2
--- /dev/null
+++ b/isa/rv32uf/fcvt.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fcvt.S"
diff --git a/isa/rv32uf/fcvt_w.S b/isa/rv32uf/fcvt_w.S
new file mode 100644
index 0000000..3447530
--- /dev/null
+++ b/isa/rv32uf/fcvt_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fcvt_w.S"
diff --git a/isa/rv32uf/fdiv.S b/isa/rv32uf/fdiv.S
new file mode 100644
index 0000000..12aaa3d
--- /dev/null
+++ b/isa/rv32uf/fdiv.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fdiv.S"
diff --git a/isa/rv32uf/fmadd.S b/isa/rv32uf/fmadd.S
new file mode 100644
index 0000000..8a5aacb
--- /dev/null
+++ b/isa/rv32uf/fmadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fmadd.S"
diff --git a/isa/rv32uf/fmin.S b/isa/rv32uf/fmin.S
new file mode 100644
index 0000000..9231d01
--- /dev/null
+++ b/isa/rv32uf/fmin.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fmin.S"
diff --git a/isa/rv32uf/fsgnj.S b/isa/rv32uf/fsgnj.S
new file mode 100644
index 0000000..6d05a23
--- /dev/null
+++ b/isa/rv32uf/fsgnj.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fsgnj.S"
diff --git a/isa/rv32uf/ldst.S b/isa/rv32uf/ldst.S
new file mode 100644
index 0000000..01f7fef
--- /dev/null
+++ b/isa/rv32uf/ldst.S
@@ -0,0 +1,38 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32UF
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a0, 0x40000000, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); lw a0, 20(a1))
+  TEST_CASE(3, a0, 0xbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); lw a0, 24(a1))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+.word 0xbf800000
+.word 0x40000000
+.word 0x40400000
+.word 0xc0800000
+.word 0xdeadbeef
+.word 0xcafebabe
+.word 0xabad1dea
+.word 0x1337d00d
+
+RVTEST_DATA_END
diff --git a/isa/rv32uf/move.S b/isa/rv32uf/move.S
new file mode 100644
index 0000000..949da6f
--- /dev/null
+++ b/isa/rv32uf/move.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/move.S"
diff --git a/isa/rv32uf/recoding.S b/isa/rv32uf/recoding.S
new file mode 100644
index 0000000..5dc0113
--- /dev/null
+++ b/isa/rv32uf/recoding.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/recoding.S"