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| author | HUJIYONG <107032865+HUJIYONG@users.noreply.github.com> | 2024-08-15 09:24:55 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-14 18:24:55 -0700 |
| commit | e2cdf460d248925b43b9085a3470102ce8a0a83b (patch) | |
| tree | 7cbb3fcf011a10291a62f600dfb106125104c654 /isa/rv32uf/fcmp.S | |
| parent | f2f748ebb9cf8ea049103f85c4cbf7e8a2927b16 (diff) | |
| download | riscv-tests-master.zip riscv-tests-master.tar.gz riscv-tests-master.tar.bz2 | |
issue#577
In the newest riscv spec(2021 or later), two csr register
"sptbr"(0x180) "s/mbadaddr"(0x243) were removed,
and upgraded to "satp" "s/mtval". Together with more functions.
This commit rename them to pass compile.
Diffstat (limited to 'isa/rv32uf/fcmp.S')
0 files changed, 0 insertions, 0 deletions