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| author | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-01-31 18:10:35 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-01-31 18:10:35 -0800 |
| commit | cdd27919a7314324aece473270364e358c89f54f (patch) | |
| tree | 032e537ec7dd2aea74f67ac484b8bfceb68133fe /isa/rv32si | |
| parent | 6ff9837501d34c1c8f87ded1fb05fe95987dba2d (diff) | |
| download | riscv-tests-cdd27919a7314324aece473270364e358c89f54f.zip riscv-tests-cdd27919a7314324aece473270364e358c89f54f.tar.gz riscv-tests-cdd27919a7314324aece473270364e358c89f54f.tar.bz2 | |
Add rv32si tests, including illegality of shamt[5]
Diffstat (limited to 'isa/rv32si')
| -rw-r--r-- | isa/rv32si/Makefrag | 15 | ||||
| -rw-r--r-- | isa/rv32si/csr.S | 14 | ||||
| -rw-r--r-- | isa/rv32si/ipi.S | 14 | ||||
| -rw-r--r-- | isa/rv32si/shamt.S | 44 |
4 files changed, 87 insertions, 0 deletions
diff --git a/isa/rv32si/Makefrag b/isa/rv32si/Makefrag new file mode 100644 index 0000000..7ffc060 --- /dev/null +++ b/isa/rv32si/Makefrag @@ -0,0 +1,15 @@ +#======================================================================= +# Makefrag for rv32si tests +#----------------------------------------------------------------------- + +rv32si_sc_tests = \ + csr \ + shamt \ + +rv32si_mc_tests = \ + ipi \ + +rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests)) +rv32si_pm_tests = $(addprefix rv32si-pm-, $(rv32si_mc_tests)) + +spike_tests += $(rv32si_p_tests) $(rv32si_pm_tests) diff --git a/isa/rv32si/csr.S b/isa/rv32si/csr.S new file mode 100644 index 0000000..c229b50 --- /dev/null +++ b/isa/rv32si/csr.S @@ -0,0 +1,14 @@ +#***************************************************************************** +# csr.S +#----------------------------------------------------------------------------- +# +# Test CSRRx and CSRRxI instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S + +#include "../rv64si/csr.S" diff --git a/isa/rv32si/ipi.S b/isa/rv32si/ipi.S new file mode 100644 index 0000000..4682bee --- /dev/null +++ b/isa/rv32si/ipi.S @@ -0,0 +1,14 @@ +#***************************************************************************** +# ipi.S +#----------------------------------------------------------------------------- +# +# Test interprocessor interrupts. +# + +#include "riscv_test.h" +#include "test_macros.h" + +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S + +#include "../rv64si/ipi.S" diff --git a/isa/rv32si/shamt.S b/isa/rv32si/shamt.S new file mode 100644 index 0000000..df97287 --- /dev/null +++ b/isa/rv32si/shamt.S @@ -0,0 +1,44 @@ +#***************************************************************************** +# csr.S +#----------------------------------------------------------------------------- +# +# Test CSRRx and CSRRxI instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32S +RVTEST_CODE_BEGIN + + la t0, evec + csrw evec, t0 + + # Make sure slli with shamt[4] set is legal. + TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16); + + # Make sure slli with shamt[4] set is not legal. + TEST_CASE( 3, x0, 1, slli a0, a0, 32); + + TEST_PASSFAIL + +evec: + # Trapping on test 3 is good. + # Note that since the test didn't complete, TESTNUM is smaller by 1. + li t0, 2 + bne TESTNUM, t0, fail + + # Make sure CAUSE indicates an illegal instructino. + csrr t0, cause + li t1, CAUSE_ILLEGAL_INSTRUCTION + bne t0, t1, fail + j pass + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END |