Merge rv64si and rv32si tests

8 files changed, 15 insertions, 286 deletions

diff --git a/isa/rv32si/csr.S b/isa/rv32si/csr.S
index 9f095c7..3c414c0 100644
--- a/isa/rv32si/csr.S
+++ b/isa/rv32si/csr.S
@@ -1,15 +1,6 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# csr.S
-#-----------------------------------------------------------------------------
-#
-# Test CSRRx and CSRRxI instructions.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
 #undef RVTEST_RV64S
 #define RVTEST_RV64S RVTEST_RV32S
 
diff --git a/isa/rv32si/illegal.S b/isa/rv32si/illegal.S
index 3bec030..ad5c3b1 100644
--- a/isa/rv32si/illegal.S
+++ b/isa/rv32si/illegal.S
@@ -1,43 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# illegal.S
-#-----------------------------------------------------------------------------
-#
-# Test illegal instruction trap.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
-
-  la t0, stvec
-  csrw stvec, t0
-
-  li TESTNUM, 2
-  .word 0
-  j fail
-
-  j pass
-
-  TEST_PASSFAIL
-
-stvec:
-  li t1, CAUSE_ILLEGAL_INSTRUCTION
-  csrr t0, scause
-  bne t0, t1, fail
-  csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
 
-RVTEST_DATA_END
+#include "../rv64si/illegal.S"
diff --git a/isa/rv32si/ipi.S b/isa/rv32si/ipi.S
index 81c33f6..7e11423 100644
--- a/isa/rv32si/ipi.S
+++ b/isa/rv32si/ipi.S
@@ -1,15 +1,6 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# ipi.S
-#-----------------------------------------------------------------------------
-#
-# Test interprocessor interrupts.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
 #undef RVTEST_RV64S
 #define RVTEST_RV64S RVTEST_RV32S
 
diff --git a/isa/rv32si/ma_addr.S b/isa/rv32si/ma_addr.S
index 13ac778..51465a2 100644
--- a/isa/rv32si/ma_addr.S
+++ b/isa/rv32si/ma_addr.S
@@ -1,89 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# ma_addr.S
-#-----------------------------------------------------------------------------
-#
-# Test misaligned ld/st trap.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
-
-  la s0, stvec_load
-
-  la t0, stvec_load
-  csrw stvec, t0
-
-  li TESTNUM, 2
-  lw x0, 1(s0)
-  j fail
-
-  li TESTNUM, 3
-  lw x0, 2(s0)
-  j fail
-
-  li TESTNUM, 4
-  lw x0, 3(s0)
-  j fail
-
-  li TESTNUM, 5
-  lh x0, 1(s0)
-  j fail
-
-  li TESTNUM, 6
-  lhu x0, 1(s0)
-  j fail
-
-  la t0, stvec_store
-  csrw stvec, t0
-
-  li TESTNUM, 7
-  sw x0, 1(s0)
-  j fail
-
-  li TESTNUM, 8
-  sw x0, 2(s0)
-  j fail
-
-  li TESTNUM, 9
-  sw x0, 3(s0)
-  j fail
-
-  li TESTNUM, 10
-  sh x0, 1(s0)
-  j fail
-
-  j pass
-
-  TEST_PASSFAIL
-
-stvec_load:
-  li t1, CAUSE_MISALIGNED_LOAD
-  csrr t0, scause
-  bne t0, t1, fail
-  csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
-
-stvec_store:
-  li t1, CAUSE_MISALIGNED_STORE
-  csrr t0, scause
-  bne t0, t1, fail
-  csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
 
-RVTEST_DATA_END
+#include "../rv64si/ma_addr.S"
diff --git a/isa/rv32si/ma_fetch.S b/isa/rv32si/ma_fetch.S
index 4aa7973..2e5254f 100644
--- a/isa/rv32si/ma_fetch.S
+++ b/isa/rv32si/ma_fetch.S
@@ -1,61 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# ma_fetch.S
-#-----------------------------------------------------------------------------
-#
-# Test misaligned fetch trap.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
-
-  la t0, stvec
-  csrw stvec, t0
-
-  li TESTNUM, 2
-  la t0, 1f
-  jr t0, 2
-1:
-  j fail
-
-  li TESTNUM, 3
-  la t0, 2f
-  jr t0, 1
-2:
-  // this test should pass, since the low bit should be masked off
-
-  li TESTNUM, 4
-  la t0, 3f
-  jr t0, 3
-3:
-  j fail
-
-  j pass
-
-  TEST_PASSFAIL
-
-stvec:
-  li t0, 3
-  beq TESTNUM, t0, fail
-
-  li t1, CAUSE_MISALIGNED_FETCH
-  csrr t0, scause
-  bne t0, t1, fail
-  li t1, 0
-  csrr t0, sepc
-  addi t0, t0, 2 // skip over instruction after jalr
-  csrw sepc, t0
-  sret
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
 
-RVTEST_DATA_END
+#include "../rv64si/ma_fetch.S"
diff --git a/isa/rv32si/sbreak.S b/isa/rv32si/sbreak.S
index cd920db..3dcfba2 100644
--- a/isa/rv32si/sbreak.S
+++ b/isa/rv32si/sbreak.S
@@ -1,43 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# scall.S
-#-----------------------------------------------------------------------------
-#
-# Test syscall trap.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
-
-  la t0, stvec
-  csrw stvec, t0
-
-  li TESTNUM, 2
-  sbreak
-  j fail
-
-  j pass
-
-  TEST_PASSFAIL
-
-stvec:
-  li t1, CAUSE_BREAKPOINT
-  csrr t0, scause
-  bne t0, t1, fail
-  csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
 
-RVTEST_DATA_END
+#include "../rv64si/sbreak.S"
diff --git a/isa/rv32si/scall.S b/isa/rv32si/scall.S
index a036aaf..5b732c8 100644
--- a/isa/rv32si/scall.S
+++ b/isa/rv32si/scall.S
@@ -1,43 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# scall.S
-#-----------------------------------------------------------------------------
-#
-# Test syscall trap.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
-
-  la t0, stvec
-  csrw stvec, t0
-
-  li TESTNUM, 2
-  scall
-  j fail
-
-  j pass
-
-  TEST_PASSFAIL
-
-stvec:
-  li t1, CAUSE_ECALL
-  csrr t0, scause
-  bne t0, t1, fail
-  csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
 
-RVTEST_DATA_END
+#include "../rv64si/scall.S"
diff --git a/isa/rv32si/timer.S b/isa/rv32si/timer.S
index 5c627d5..a6847aa 100644
--- a/isa/rv32si/timer.S
+++ b/isa/rv32si/timer.S
@@ -1,15 +1,6 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# timer.S
-#-----------------------------------------------------------------------------
-#
-# Test timer interrupt.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
 #undef RVTEST_RV64S
 #define RVTEST_RV64S RVTEST_RV32S