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| author | Megan Wachs <megan@sifive.com> | 2018-04-27 16:52:43 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-04-27 16:52:43 -0700 |
| commit | 65b4e2e93c7cee0a53143c661e1347363e6d6194 (patch) | |
| tree | 950e792262543fe60f46adfccce5c3c27aae15e3 /isa/rv32mi | |
| parent | bfa3b7d34bca67435d91786a81c9df8963bcccae (diff) | |
| download | riscv-tests-debug-clear-satp.zip riscv-tests-debug-clear-satp.tar.gz riscv-tests-debug-clear-satp.tar.bz2 | |
debug: need to clear satp before changing privdebug-clear-satp
ISA Manual does not require this register to be reset, and attempting to execute code with VM on when VM hasn't been set up is going to just lead to sadness.
Diffstat (limited to 'isa/rv32mi')
0 files changed, 0 insertions, 0 deletions