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author | Andrew Waterman <andrew@sifive.com> | 2024-02-18 20:09:30 -0800 |
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committer | GitHub <noreply@github.com> | 2024-02-18 20:09:30 -0800 |
commit | 3bd02c8ab45666cf1c0532294f115c4d2ce3e027 (patch) | |
tree | 1a5653d944c240bb81dbfa4c37e922186af35215 /isa/Makefile | |
parent | ad33ed3cb50b4cc23a44657a541f76325e659af0 (diff) | |
parent | 9c06101326cdd451a051bc3e6469b3c76f24d101 (diff) | |
download | riscv-tests-3bd02c8ab45666cf1c0532294f115c4d2ce3e027.zip riscv-tests-3bd02c8ab45666cf1c0532294f115c4d2ce3e027.tar.gz riscv-tests-3bd02c8ab45666cf1c0532294f115c4d2ce3e027.tar.bz2 |
Merge pull request #539 from rogerchang23424/bitmanip
Add bitmanip test cases
Diffstat (limited to 'isa/Makefile')
-rw-r--r-- | isa/Makefile | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/isa/Makefile b/isa/Makefile index d66b901..bf85e1f 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -14,6 +14,10 @@ include $(src_dir)/rv64ua/Makefrag include $(src_dir)/rv64uf/Makefrag include $(src_dir)/rv64ud/Makefrag include $(src_dir)/rv64uzfh/Makefrag +include $(src_dir)/rv64uzba/Makefrag +include $(src_dir)/rv64uzbb/Makefrag +include $(src_dir)/rv64uzbc/Makefrag +include $(src_dir)/rv64uzbs/Makefrag include $(src_dir)/rv64si/Makefrag include $(src_dir)/rv64ssvnapot/Makefrag include $(src_dir)/rv64mi/Makefrag @@ -26,6 +30,10 @@ include $(src_dir)/rv32ua/Makefrag include $(src_dir)/rv32uf/Makefrag include $(src_dir)/rv32ud/Makefrag include $(src_dir)/rv32uzfh/Makefrag +include $(src_dir)/rv32uzba/Makefrag +include $(src_dir)/rv32uzbb/Makefrag +include $(src_dir)/rv32uzbc/Makefrag +include $(src_dir)/rv32uzbs/Makefrag include $(src_dir)/rv32si/Makefrag include $(src_dir)/rv32mi/Makefrag @@ -50,10 +58,10 @@ vpath %.S $(src_dir) $(RISCV_OBJDUMP) $< > $@ %.out: % - $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@ %.out32: % - $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@ define compile_template @@ -86,6 +94,10 @@ $(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32)) +$(eval $(call compile_template,rv32uzba,-march=rv32g_zba -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbb,-march=rv32g_zbb -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbc,-march=rv32g_zbc -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbs,-march=rv32g_zbs -mabi=ilp32)) $(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32)) ifeq ($(XLEN),64) @@ -96,6 +108,10 @@ $(eval $(call compile_template,rv64ua,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64)) +$(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64)) +$(eval $(call compile_template,rv64uzbb,-march=rv64g_zbb -mabi=lp64)) +$(eval $(call compile_template,rv64uzbc,-march=rv64g_zbc -mabi=lp64)) +$(eval $(call compile_template,rv64uzbs,-march=rv64g_zbs -mabi=lp64)) $(eval $(call compile_template,rv64mzicbo,-march=rv64g_zicboz -mabi=lp64)) $(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64)) |