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author | Jerry Zhao <jerryz123@berkeley.edu> | 2024-06-24 15:19:59 -0700 |
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committer | GitHub <noreply@github.com> | 2024-06-24 15:19:59 -0700 |
commit | e06a435c1e545def71e833031356372f0828f165 (patch) | |
tree | 08481e02b8935dcef8574fcdf1ebbe87066a9e03 /debug | |
parent | 1d3c10c06e5258711041fde95adefcb1b069aaf6 (diff) | |
download | riscv-tests-e06a435c1e545def71e833031356372f0828f165.zip riscv-tests-e06a435c1e545def71e833031356372f0828f165.tar.gz riscv-tests-e06a435c1e545def71e833031356372f0828f165.tar.bz2 |
Use Zvl/Zve to communicate VLEN/ELEN to target in debug tests (#567)
Diffstat (limited to 'debug')
-rwxr-xr-x | debug/test | bin | 0 -> 17704 bytes | |||
-rw-r--r-- | debug/testlib.py | 5 |
2 files changed, 3 insertions, 2 deletions
diff --git a/debug/test b/debug/test Binary files differnew file mode 100755 index 0000000..9b72737 --- /dev/null +++ b/debug/test diff --git a/debug/testlib.py b/debug/testlib.py index 1f107be..41d9cea 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -134,6 +134,9 @@ class Spike: else: isa = f"RV{self.harts[0].xlen}G" + if 'V' in isa[2:]: + isa += f"_Zvl{self.vlen}b_Zve{self.elen}d" + cmd += ["--isa", isa] cmd += ["--dm-auth"] @@ -159,8 +162,6 @@ class Spike: if not self.support_haltgroups: cmd.append("--dm-no-halt-groups") - if 'V' in isa[2:]: - cmd.append(f"--varch=vlen:{self.vlen},elen:{self.elen}") assert len(set(t.ram for t in self.harts)) == 1, \ "All spike harts must have the same RAM layout" |