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authorTim Newsome <tim@sifive.com>2023-05-03 11:11:19 -0700
committerGitHub <noreply@github.com>2023-05-03 11:11:19 -0700
commit9e0adec703248c2fd8ae5b14ae64db8d1249c96c (patch)
treecf3f62a6cb4aba8d098d9967a5c01add6f093d79 /debug
parent394937eceb62bc4ba8ad5a4e916f0508d9803229 (diff)
parent2df94d84afea3a75719187da68656b43f53ce957 (diff)
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Merge pull request #469 from riscv-software-src/openocd_cfg
Update OpenOCD cfg files to new syntax
Diffstat (limited to 'debug')
-rw-r--r--debug/targets/RISC-V/spike-1.cfg10
-rw-r--r--debug/targets/RISC-V/spike-2-hwthread.cfg10
-rw-r--r--debug/targets/RISC-V/spike-2.cfg10
-rw-r--r--debug/targets/RISC-V/spike-multi.cfg12
-rw-r--r--debug/targets/SiFive/Freedom/Freedom.cfg2
-rw-r--r--debug/targets/SiFive/HiFive1.cfg12
-rw-r--r--debug/targets/SiFive/HiFiveUnleashed.cfg12
7 files changed, 34 insertions, 34 deletions
diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg
index 5f11b08..c6c7d2d 100644
--- a/debug/targets/RISC-V/spike-1.cfg
+++ b/debug/targets/RISC-V/spike-1.cfg
@@ -1,8 +1,8 @@
-adapter_khz 10000
+adapter speed 10000
-interface remote_bitbang
-remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
-remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+adapter driver remote_bitbang
+remote_bitbang host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang port $::env(REMOTE_BITBANG_PORT)
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
@@ -26,7 +26,7 @@ riscv expose_custom 1,12345-12348
init
set challenge [riscv authdata_read]
-riscv authdata_write [expr $challenge + 1]
+riscv authdata_write [expr {$challenge + 1}]
halt
diff --git a/debug/targets/RISC-V/spike-2-hwthread.cfg b/debug/targets/RISC-V/spike-2-hwthread.cfg
index dc60ced..c10ad8f 100644
--- a/debug/targets/RISC-V/spike-2-hwthread.cfg
+++ b/debug/targets/RISC-V/spike-2-hwthread.cfg
@@ -1,9 +1,9 @@
# Connect to a mult-icore RISC-V target, exposing each hart as a thread.
-adapter_khz 10000
+adapter speed 10000
-interface remote_bitbang
-remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
-remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+adapter driver remote_bitbang
+remote_bitbang host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang port $::env(REMOTE_BITBANG_PORT)
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
@@ -30,7 +30,7 @@ riscv resume_order reversed
init
set challenge [riscv authdata_read]
-riscv authdata_write [expr $challenge + 1]
+riscv authdata_write [expr {$challenge + 1}]
halt
diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg
index 640fba9..ebf3c5a 100644
--- a/debug/targets/RISC-V/spike-2.cfg
+++ b/debug/targets/RISC-V/spike-2.cfg
@@ -1,9 +1,9 @@
# Connect to a mult-icore RISC-V target, exposing each hart as a thread.
-adapter_khz 10000
+adapter speed 10000
-interface remote_bitbang
-remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
-remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+adapter driver remote_bitbang
+remote_bitbang host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang port $::env(REMOTE_BITBANG_PORT)
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
@@ -27,7 +27,7 @@ foreach t [target names] {
init
set challenge [riscv authdata_read]
-riscv authdata_write [expr $challenge + 1]
+riscv authdata_write [expr {$challenge + 1}]
foreach t [target names] {
targets $t
diff --git a/debug/targets/RISC-V/spike-multi.cfg b/debug/targets/RISC-V/spike-multi.cfg
index ef6dfc6..36d4328 100644
--- a/debug/targets/RISC-V/spike-multi.cfg
+++ b/debug/targets/RISC-V/spike-multi.cfg
@@ -1,9 +1,9 @@
# Connect to a mult-icore RISC-V target, exposing each hart as a thread.
-adapter_khz 10000
+adapter speed 10000
-interface remote_bitbang
-remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
-remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+adapter driver remote_bitbang
+remote_bitbang host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang port $::env(REMOTE_BITBANG_PORT)
jtag newtap riscv.0 cpu -irlen 5 -expected-id 0x10e31913
jtag newtap riscv.1 cpu -irlen 5 -expected-id 0x10e31913
@@ -33,11 +33,11 @@ init
targets riscv.0.cpu0
set challenge [riscv authdata_read]
-riscv authdata_write [expr $challenge + 1]
+riscv authdata_write [expr {$challenge + 1}]
targets riscv.1.cpu0
set challenge [riscv authdata_read]
-riscv authdata_write [expr $challenge + 1]
+riscv authdata_write [expr {$challenge + 1}]
foreach t [target names] {
targets $t
diff --git a/debug/targets/SiFive/Freedom/Freedom.cfg b/debug/targets/SiFive/Freedom/Freedom.cfg
index 8947bf5..c85aa08 100644
--- a/debug/targets/SiFive/Freedom/Freedom.cfg
+++ b/debug/targets/SiFive/Freedom/Freedom.cfg
@@ -1,4 +1,4 @@
-adapter_khz 10000
+adapter speed 10000
source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
diff --git a/debug/targets/SiFive/HiFive1.cfg b/debug/targets/SiFive/HiFive1.cfg
index 333c82e..e23d3f0 100644
--- a/debug/targets/SiFive/HiFive1.cfg
+++ b/debug/targets/SiFive/HiFive1.cfg
@@ -1,11 +1,11 @@
-adapter_khz 10000
+adapter speed 10000
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
-ftdi_layout_init 0x0008 0x001b
-ftdi_layout_signal nSRST -oe 0x0020
+ftdi layout_init 0x0008 0x001b
+ftdi layout_signal nSRST -oe 0x0020
# ...
diff --git a/debug/targets/SiFive/HiFiveUnleashed.cfg b/debug/targets/SiFive/HiFiveUnleashed.cfg
index 3d20be0..e88b9b4 100644
--- a/debug/targets/SiFive/HiFiveUnleashed.cfg
+++ b/debug/targets/SiFive/HiFiveUnleashed.cfg
@@ -1,11 +1,11 @@
-adapter_khz 10000
+adapter speed 10000
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
+adapter driver ftdi
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
-ftdi_layout_init 0x0008 0x001b
-ftdi_layout_signal nSRST -oe 0x0020
+ftdi layout_init 0x0008 0x001b
+ftdi layout_signal nSRST -oe 0x0020
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913