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| author | Tim Newsome <tim@sifive.com> | 2017-08-07 12:51:42 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-08-28 12:16:39 -0700 |
| commit | 3a44725d27f6b2c77f0ca912d792b6856fde6a17 (patch) | |
| tree | e89d52105aa01d59e7d4588ef157d477f0a4335d /debug/targets/SiFive/HiFive1.py | |
| parent | ab6c2ccaec192684cf4649d5d69bd105d738d1c7 (diff) | |
| download | riscv-tests-3a44725d27f6b2c77f0ca912d792b6856fde6a17.zip riscv-tests-3a44725d27f6b2c77f0ca912d792b6856fde6a17.tar.gz riscv-tests-3a44725d27f6b2c77f0ca912d792b6856fde6a17.tar.bz2 | |
Make the debug tests aware of multicore.
Targets now contain an array of harts. When running a regular test, one
hart is selected to run the test on while the remaining harts are parked
in a safe infinite loop.
There's currently only one test that tests multicore behavior, but there
could be more.
The infrastructure should be able to support heterogeneous multicore,
but I don't have a target like that to test with.
Diffstat (limited to 'debug/targets/SiFive/HiFive1.py')
| -rw-r--r-- | debug/targets/SiFive/HiFive1.py | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/debug/targets/SiFive/HiFive1.py b/debug/targets/SiFive/HiFive1.py index 813829e..3cb508c 100644 --- a/debug/targets/SiFive/HiFive1.py +++ b/debug/targets/SiFive/HiFive1.py @@ -1,8 +1,11 @@ import targets -class HiFive1(targets.Target): +class HiFive1Hart(targets.Hart): xlen = 32 ram = 0x80000000 ram_size = 16 * 1024 instruction_hardware_breakpoint_count = 2 misa = 0x40001105 + +class HiFive1(targets.Target): + harts = [HiFive1Hart()] |