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| author | Tim Newsome <tim@sifive.com> | 2017-10-05 12:48:40 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-10-05 12:48:40 -0700 |
| commit | cad03ed0e58693257176ebaf4cbb70484a44fd2e (patch) | |
| tree | cdd02426a6a429c2ac5ebf4d781b3519ea0c63f4 /debug/targets/RISC-V/spike-rtos.cfg | |
| parent | 5eb2cf39af91f9d886e28175b729f02684c27df4 (diff) | |
| parent | 9091137e4a4797a91179ab73886697c7fe270da2 (diff) | |
| download | riscv-tests-interrupts.zip riscv-tests-interrupts.tar.gz riscv-tests-interrupts.tar.bz2 | |
Merge branch 'master' into interruptsinterrupts
Diffstat (limited to 'debug/targets/RISC-V/spike-rtos.cfg')
| -rw-r--r-- | debug/targets/RISC-V/spike-rtos.cfg | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg new file mode 100644 index 0000000..799e3cb --- /dev/null +++ b/debug/targets/RISC-V/spike-rtos.cfg @@ -0,0 +1,17 @@ +# Connect to a mult-icore RISC-V target, exposing each hart as a thread. +adapter_khz 10000 + +interface remote_bitbang +remote_bitbang_host $::env(REMOTE_BITBANG_HOST) +remote_bitbang_port $::env(REMOTE_BITBANG_PORT) + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv + +gdb_report_data_abort enable + +init +reset halt |