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authorTim Newsome <tim@sifive.com>2018-02-27 14:28:26 -0800
committerTim Newsome <tim@sifive.com>2018-02-27 14:28:26 -0800
commitdb31c3dd894bca1e7aed903a159cf0e794f177c0 (patch)
treea5c7cade840b119882b46e42b4dd6bed752f91b9 /debug/targets/RISC-V/spike-2.cfg
parentba39c5fc2885eb1400d6f9e13ae6c7588c1c1241 (diff)
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Test debug authentication.debug_auth
Also halt instead of reset spike targets, which tests a more complicated code path.
Diffstat (limited to 'debug/targets/RISC-V/spike-2.cfg')
-rw-r--r--debug/targets/RISC-V/spike-2.cfg9
1 files changed, 8 insertions, 1 deletions
diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg
index 17526ec..e2bda12 100644
--- a/debug/targets/RISC-V/spike-2.cfg
+++ b/debug/targets/RISC-V/spike-2.cfg
@@ -16,4 +16,11 @@ target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
gdb_report_data_abort enable
init
-reset halt
+
+set challenge [ocd_riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+targets $_TARGETNAME_0
+halt
+targets $_TARGETNAME_1
+halt