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author | Tim Newsome <tim@sifive.com> | 2017-06-15 12:58:40 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2017-06-15 12:58:40 -0700 |
commit | e9d129ab0fd2c2ce9e5ce4a409bacbf1b0b3a81c (patch) | |
tree | 5d3279a927a21b28e4a77f62025c15a02e0e8c5d /debug/targets.py | |
parent | 9ce37f9542f2a38edc837c1d05f4a19c18580cc4 (diff) | |
download | riscv-tests-e9d129ab0fd2c2ce9e5ce4a409bacbf1b0b3a81c.zip riscv-tests-e9d129ab0fd2c2ce9e5ce4a409bacbf1b0b3a81c.tar.gz riscv-tests-e9d129ab0fd2c2ce9e5ce4a409bacbf1b0b3a81c.tar.bz2 |
Test 64-bit addressing.
The spike64 target now links all test programs at 0x7fff_ffff_ffff_0000.
Also a minor change to log file naming so that 'make all' works again.
I'll fix this better later.
Diffstat (limited to 'debug/targets.py')
-rw-r--r-- | debug/targets.py | 24 |
1 files changed, 17 insertions, 7 deletions
diff --git a/debug/targets.py b/debug/targets.py index bd177ec..525561e 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -60,31 +60,41 @@ class Target(object): def extensionSupported(self, letter): # target.misa is set by testlib.ExamineTarget - return self.misa & (1 << (ord(letter.upper()) - ord('A'))) + if self.misa: + return self.misa & (1 << (ord(letter.upper()) - ord('A'))) + else: + return False class SpikeTarget(Target): # pylint: disable=abstract-method - directory = "spike" - ram = 0x10000000 - ram_size = 0x10000000 instruction_hardware_breakpoint_count = 4 reset_vector = 0x1000 - openocd_config = "targets/%s/openocd.cfg" % directory class Spike64Target(SpikeTarget): name = "spike64" + directory = name xlen = 64 use_fpu = True + # Would like to use 0x7fffffffffff0000 because it crosses the 0x8000... + # boundary, but spike doesn't support that in the code where it generates + # the reset vector. + ram = 0x1212340000 + ram_size = 0x10000000 + openocd_config = "targets/%s/openocd.cfg" % directory def target(self): - return testlib.Spike(self.sim_cmd) + return testlib.Spike(self) class Spike32Target(SpikeTarget): name = "spike32" + directory = name xlen = 32 + ram = 0x10000000 + ram_size = 0x10000000 + openocd_config = "targets/%s/openocd.cfg" % directory def target(self): - return testlib.Spike(self.sim_cmd, xlen=32) + return testlib.Spike(self) class FreedomE300Target(Target): name = "freedom-e300" |