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| author | Tim Newsome <tim@sifive.com> | 2020-12-31 12:48:19 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2020-12-31 12:48:19 -0800 |
| commit | 7d069666a5841e5e5b3ba1723c6af26925a35a9c (patch) | |
| tree | c4c87bce99b8f2ce58a74e7250dbb1eeb778d78f /debug/targets.py | |
| parent | 3496243928e3dbd562dd84bcf9e6222221d423e5 (diff) | |
| download | riscv-tests-7d069666a5841e5e5b3ba1723c6af26925a35a9c.zip riscv-tests-7d069666a5841e5e5b3ba1723c6af26925a35a9c.tar.gz riscv-tests-7d069666a5841e5e5b3ba1723c6af26925a35a9c.tar.bz2 | |
Make HiFiveUnleashed tests clean.
HiFiveUnleashed-flash fails som address translation tests. Possibly that
would be fixed when https://github.com/riscv/riscv-tests/pull/313
merges.
Diffstat (limited to 'debug/targets.py')
| -rw-r--r-- | debug/targets.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/debug/targets.py b/debug/targets.py index be5c9fa..e9fb4f6 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -28,6 +28,10 @@ class Hart: ram = None ram_size = None + # Address where we expect memory accesses to fail, usually because there is + # no device mapped to that location. + bad_address = None + # Number of instruction triggers the hart supports. instruction_hardware_breakpoint_count = 0 |