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| author | liangzhen <zhen.liang@spacemit.com> | 2023-10-16 10:53:02 +0800 |
|---|---|---|
| committer | liangzhen <zhen.liang@spacemit.com> | 2023-10-17 09:17:11 +0800 |
| commit | 57544c2c89f720015ca6c25ca1632603ab712901 (patch) | |
| tree | d6355e4f8c0dd6545f1b4139c97d8a095ab3a79a /debug/targets.py | |
| parent | c36c814ae49610bc407a5c4e144866fa50e4510e (diff) | |
| download | riscv-tests-57544c2c89f720015ca6c25ca1632603ab712901.zip riscv-tests-57544c2c89f720015ca6c25ca1632603ab712901.tar.gz riscv-tests-57544c2c89f720015ca6c25ca1632603ab712901.tar.bz2 | |
Make the non-existent csr configurable
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
Diffstat (limited to 'debug/targets.py')
| -rw-r--r-- | debug/targets.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/debug/targets.py b/debug/targets.py index 3f63e79..c1633e9 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -33,6 +33,9 @@ class Hart: # no device mapped to that location. bad_address = None + # The non-existent register for access test + nonexist_csr = "csr2288" + # Number of instruction triggers the hart supports. instruction_hardware_breakpoint_count = 0 |