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| author | Megan Wachs <megan@sifive.com> | 2016-08-04 14:21:37 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2016-08-08 11:48:02 -0700 |
| commit | 1d9383f6a7b1a31406dd86adc0975775eb1442a1 (patch) | |
| tree | 104b0244255b2894748bc3912f01b274d5d16e89 /debug/README.md | |
| parent | 99ea2bfc87739eb62a8eb1012e6b38d123feede5 (diff) | |
| download | riscv-tests-1d9383f6a7b1a31406dd86adc0975775eb1442a1.zip riscv-tests-1d9383f6a7b1a31406dd86adc0975775eb1442a1.tar.gz riscv-tests-1d9383f6a7b1a31406dd86adc0975775eb1442a1.tar.bz2 | |
Added FreedomE300 Simulator target
Diffstat (limited to 'debug/README.md')
| -rw-r--r-- | debug/README.md | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/debug/README.md b/debug/README.md index 4a90c0c..8424b87 100644 --- a/debug/README.md +++ b/debug/README.md @@ -19,11 +19,17 @@ Targets `./gdbserver.py --spike32 --cmd $RISCV/bin/spike` -32-bit SiFive Core on Arty FPGA board +32-bit SiFive Core on Supported FPGA boards ------------------------------------- `./gdbserver.py --freedom-e300` +32-bit rocket-chip core in Simulation +------------------------------------- + +`./gdbserver.py --freedom-e300-sim` + + Debug Tips ========== |