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author | Palmer Dabbelt <palmer@dabbelt.com> | 2016-07-12 09:19:08 -0700 |
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committer | Palmer Dabbelt <palmer@dabbelt.com> | 2016-07-12 09:19:08 -0700 |
commit | 00df2be7a414d34c7633142c73ac6130f6cbbd4b (patch) | |
tree | 49ade5408f077f851fd90280fc300709148883f9 /benchmarks/common/crt.S | |
parent | d82a880f81cb5d197f712bbd17e821e0d70d7b75 (diff) | |
parent | 3dc00e7b04834f862a074ac8822892e1ecfc009c (diff) | |
download | riscv-tests-smi-demo.zip riscv-tests-smi-demo.tar.gz riscv-tests-smi-demo.tar.bz2 |
Merge commit '3dc00e7' into smi-demosmi-demo
Diffstat (limited to 'benchmarks/common/crt.S')
-rw-r--r-- | benchmarks/common/crt.S | 27 |
1 files changed, 12 insertions, 15 deletions
diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S index 7c8fc19..2dda05b 100644 --- a/benchmarks/common/crt.S +++ b/benchmarks/common/crt.S @@ -50,29 +50,26 @@ _start: li x30,0 li x31,0 - li t0, MSTATUS_FS; csrs mstatus, t0 # enable FPU - li t0, MSTATUS_XS; csrs mstatus, t0 # enable accelerator + # enable FPU and accelerator if present + li t0, MSTATUS_FS | MSTATUS_XS + csrs mstatus, t0 -#ifdef __riscv64 + # make sure XLEN agrees with compilation choice csrr t0, misa - # make sure processor supports RV64 if this was compiled for RV64 +#ifdef __riscv64 bltz t0, 1f +#else + bgez t0, 1f +#endif li a0, 1234 j tohost_exit 1: -#endif - - csrr t0, mstatus - li t1, MSTATUS_XS - and t1, t0, t1 - sw t1, have_vec, t2 - - ## if that didn't stick, we don't have a FPU, so don't initialize it - li t1, MSTATUS_FS - and t1, t0, t1 - beqz t1, 1f #ifdef __riscv_hard_float + # initialize FPU if we have one + andi t0, t0, 1 << ('f' - 'a') + beqz t0, 1f + fssr x0 fmv.s.x f0, x0 fmv.s.x f1, x0 |