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| author | liangzhen <zhen.liang@spacemit.com> | 2023-10-16 13:47:52 +0800 |
|---|---|---|
| committer | liangzhen <zhen.liang@spacemit.com> | 2023-10-16 13:47:52 +0800 |
| commit | 4dfd2e7b4b6ef3f1dc134d299cc2ea4d2bbadab1 (patch) | |
| tree | ba118d19cf517afb88cc6795b7937bd2f7777b94 | |
| parent | c36c814ae49610bc407a5c4e144866fa50e4510e (diff) | |
| download | riscv-tests-4dfd2e7b4b6ef3f1dc134d299cc2ea4d2bbadab1.zip riscv-tests-4dfd2e7b4b6ef3f1dc134d299cc2ea4d2bbadab1.tar.gz riscv-tests-4dfd2e7b4b6ef3f1dc134d299cc2ea4d2bbadab1.tar.bz2 | |
Make CLINT address configurable
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
| -rwxr-xr-x | debug/gdbserver.py | 6 | ||||
| -rw-r--r-- | debug/programs/init.h | 6 | ||||
| -rw-r--r-- | debug/programs/run_halt_timing.S | 6 | ||||
| -rw-r--r-- | debug/targets.py | 6 |
4 files changed, 17 insertions, 7 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 3a6f932..e48b888 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -912,7 +912,7 @@ class RepeatReadTest(DebugTest): def test(self): self.gdb.b("main:start") self.gdb.c() - mtime_addr = 0x02000000 + 0xbff8 + mtime_addr = self.target.clint_addr + 0xbff8 count = 1024 output = self.gdb.command( f"monitor riscv repeat_read {count} 0x{mtime_addr:x} 4") @@ -1048,8 +1048,8 @@ class InterruptTest(GdbSingleHartTest): def postMortem(self): GdbSingleHartTest.postMortem(self) - self.gdb.p("*((long long*) 0x200bff8)") - self.gdb.p("*((long long*) 0x2004000)") + self.gdb.p(f"*((long long*) 0x{self.target.clint_addr + 0xbff8:x})") + self.gdb.p(f"*((long long*) 0x{self.target.clint_addr + 0x4000:x})") self.gdb.p("interrupt_count") self.gdb.p("local") diff --git a/debug/programs/init.h b/debug/programs/init.h index 06d5384..e79681d 100644 --- a/debug/programs/init.h +++ b/debug/programs/init.h @@ -1,8 +1,10 @@ #ifndef INIT_H #define INIT_H -#define MTIME (*(volatile long long *)(0x02000000 + 0xbff8)) -#define MTIMECMP ((volatile long long *)(0x02000000 + 0x4000)) +#ifdef CLINT +#define MTIME (*(volatile long long *)(CLINT + 0xbff8)) +#define MTIMECMP ((volatile long long *)(CLINT + 0x4000)) +#endif typedef void* (*trap_handler_t)(unsigned hartid, unsigned mcause, void *mepc, void *sp); diff --git a/debug/programs/run_halt_timing.S b/debug/programs/run_halt_timing.S index ce4000a..dc5d58b 100644 --- a/debug/programs/run_halt_timing.S +++ b/debug/programs/run_halt_timing.S @@ -8,10 +8,14 @@ # define REGBYTES 4 #endif +#ifdef CLINT +#define MTIME_ADDR CLINT + 0xbff8 +#endif + .global main main: li s0, 0 - li s1, 0x0200bff8 + li s1, MTIME_ADDR loop: addi s0, s0, 1 LREG s2, 0(s1) diff --git a/debug/targets.py b/debug/targets.py index 3f63e79..081e2c6 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -93,9 +93,12 @@ class Target: # before starting the test. gdb_setup = [] - # Supports mtime at 0x2004000 + # Supports mtime default at clint_addr + 0x4000 supports_clint_mtime = True + # CLINT register address, set to the default value of spike. + clint_addr = 0x02000000 + # Implements custom debug registers like spike does. It seems unlikely any # hardware will every do that. implements_custom_test = False @@ -189,6 +192,7 @@ class Target: Target.temporary_files.append(self.temporary_binary) args = list(sources) + [ + f"-DCLINT={self.clint_addr}", "programs/entry.S", "programs/init.c", f"-DNHARTS={len(self.harts)}", "-I", "../env", |