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| author | Tim Newsome <tim@sifive.com> | 2018-03-01 15:05:45 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-03-01 15:05:45 -0800 |
| commit | 208298c733a0e5ba9e4f7f892123745bdc7156c1 (patch) | |
| tree | 6cb350b713f7e5c50d8836a0e61feb442b797bbe | |
| parent | 8f9f628b84826b7fbd1d91b24c56f634cef91cf4 (diff) | |
| download | riscv-tests-208298c733a0e5ba9e4f7f892123745bdc7156c1.zip riscv-tests-208298c733a0e5ba9e4f7f892123745bdc7156c1.tar.gz riscv-tests-208298c733a0e5ba9e4f7f892123745bdc7156c1.tar.bz2 | |
Ensure an error when reading a non-existent CSR.
| -rwxr-xr-x | debug/gdbserver.py | 13 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike-1.cfg | 4 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike-2.cfg | 4 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike-rtos.cfg | 4 | ||||
| -rw-r--r-- | debug/targets/SiFive/HiFive1.cfg | 4 |
5 files changed, 29 insertions, 0 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index f0385d5..c7bfbf0 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -136,6 +136,19 @@ class SimpleF18Test(SimpleRegisterTest): def test(self): self.check_reg("f18", "fs2") +class SimpleNoExistTest(GdbTest): + def test(self): + try: + self.gdb.p("$csr2288") + assert False, "Reading csr2288 should have failed" + except testlib.CouldNotFetch: + pass + try: + self.gdb.p("$csr2288=5") + assert False, "Writing csr2288 should have failed" + except testlib.CouldNotFetch: + pass + class SimpleMemoryTest(GdbTest): def access_test(self, size, data_type): assertEqual(self.gdb.p("sizeof(%s)" % data_type), size) diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg index fc20b53..7607b46 100644 --- a/debug/targets/RISC-V/spike-1.cfg +++ b/debug/targets/RISC-V/spike-1.cfg @@ -12,5 +12,9 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME gdb_report_data_abort enable +# Expose an unimplemented CSR so we can test non-existent register access +# behavior. +riscv expose_csrs 2288 + init reset halt diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg index 17526ec..c78cf8f 100644 --- a/debug/targets/RISC-V/spike-2.cfg +++ b/debug/targets/RISC-V/spike-2.cfg @@ -15,5 +15,9 @@ target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 gdb_report_data_abort enable +# Expose an unimplemented CSR so we can test non-existent register access +# behavior. +riscv expose_csrs 2288 + init reset halt diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg index 799e3cb..5a70f52 100644 --- a/debug/targets/RISC-V/spike-rtos.cfg +++ b/debug/targets/RISC-V/spike-rtos.cfg @@ -13,5 +13,9 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv gdb_report_data_abort enable +# Expose an unimplemented CSR so we can test non-existent register access +# behavior. +riscv expose_csrs 2288 + init reset halt diff --git a/debug/targets/SiFive/HiFive1.cfg b/debug/targets/SiFive/HiFive1.cfg index 5bde59b..8f21b47 100644 --- a/debug/targets/SiFive/HiFive1.cfg +++ b/debug/targets/SiFive/HiFive1.cfg @@ -17,6 +17,10 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1 #-rtos riscv +# Expose an unimplemented CSR so we can test non-existent register access +# behavior. +riscv expose_csrs 2288 + flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME init #reset |