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| author | Tim Newsome <tim@sifive.com> | 2017-11-19 20:54:14 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-11-19 20:54:14 -0800 |
| commit | 8e0f6a0b1a33d35f2248628af7333ede093341d0 (patch) | |
| tree | 7378eb90594b13f19c834133fadb307238941e21 | |
| parent | 3714cacfdd8f1a20f58e7e217e1d737cecdf5340 (diff) | |
| download | riscv-tests-8e0f6a0b1a33d35f2248628af7333ede093341d0.zip riscv-tests-8e0f6a0b1a33d35f2248628af7333ede093341d0.tar.gz riscv-tests-8e0f6a0b1a33d35f2248628af7333ede093341d0.tar.bz2 | |
Make pylint happy.
| -rwxr-xr-x | debug/gdbserver.py | 3 | ||||
| -rw-r--r-- | debug/targets.py | 20 | ||||
| -rw-r--r-- | debug/testlib.py | 5 |
3 files changed, 16 insertions, 12 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 09938d3..49e42e7 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -817,7 +817,8 @@ class PrivRw(PrivTest): # Disable physical memory protection by allowing U mode access to all # memory. self.gdb.p("$pmpcfg0=0xf") # TOR, R, W, X - self.gdb.p("$pmpaddr0=0x%x" % ((self.hart.ram + self.hart.ram_size) >> 2)) + self.gdb.p("$pmpaddr0=0x%x" % + ((self.hart.ram + self.hart.ram_size) >> 2)) # Leave the PC at _start, where the first 4 instructions should be # legal in any mode. diff --git a/debug/targets.py b/debug/targets.py index 1401f1d..2cdbb33 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -153,10 +153,10 @@ def add_target_options(parser): help="The command to use to start the debug server (e.g. OpenOCD)") xlen_group = parser.add_mutually_exclusive_group() - xlen_group.add_argument("--32", action="store_const", const=32, dest="xlen", default=0, - help="Force the target to be 32-bit.") - xlen_group.add_argument("--64", action="store_const", const=64, dest="xlen", default=0, - help="Force the target to be 64-bit.") + xlen_group.add_argument("--32", action="store_const", const=32, + dest="xlen", default=0, help="Force the target to be 32-bit.") + xlen_group.add_argument("--64", action="store_const", const=64, + dest="xlen", default=0, help="Force the target to be 64-bit.") parser.add_argument("--isolate", action="store_true", help="Try to run in such a way that multiple instances can run at " @@ -180,11 +180,13 @@ def target(parsed): t = found[0](parsed.target, parsed) assert t.harts, "%s doesn't have any harts defined!" % t.name - if (parsed.xlen > 0): - for h in t.harts : - if (h.xlen == 0): + if parsed.xlen > 0: + for h in t.harts: + if h.xlen == 0: h.xlen = parsed.xlen - elif (h.xlen != parsed.xlen): - raise Exception("The target hart specified an XLEN of %d, but the command line specified an XLEN of %d. They must match." % (h.xlen, parsed.xlen)) + elif h.xlen != parsed.xlen: + raise Exception("The target hart specified an XLEN of %d, but "\ + "the command line specified an XLEN of %d. They must "\ + "match." % (h.xlen, parsed.xlen)) return t diff --git a/debug/testlib.py b/debug/testlib.py index b19eafc..90702bf 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -836,8 +836,9 @@ class ExamineTarget(GdbTest): raise TestFailed("Couldn't determine XLEN from $misa (0x%x)" % self.hart.misa) - if (misa_xlen != hart.xlen): - raise TestFailed("MISA reported XLEN of %d but we were expecting XLEN of %d\n" % (misa_xlen, hart.xlen)) + if misa_xlen != hart.xlen: + raise TestFailed("MISA reported XLEN of %d but we were "\ + "expecting XLEN of %d\n" % (misa_xlen, hart.xlen)) txt += ("%d" % misa_xlen) |